[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

[Pengcheng Wang via llvm-commits]

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@@ -106,6 +106,7 @@ Changes to the RISC-V Backend
 * `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
   the required alignment space with a sequence of `0x0` bytes (the requested
   fill value) rather than NOPs.
+* Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64``
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wangpc-pp wrote:

This should be in `clang/docs/ReleaseNotes.rst` not llvm?

https://github.com/llvm/llvm-project/pull/101321