[llvm] [RISCV] Mark all registers marked isConstant as reserved (PR #96002)

[Francis Visoiu Mistrih via llvm-commits]

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@@ -104,14 +104,16 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
-  // Mark any registers requested to be reserved as such
   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
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francisvm wrote:

I went with iterating from `RISCV::NoRegister` to `RISCV::NUM_TARGET_REGS`, with a GPR check before calling `Subtarget.isRegisterReservedByUser`.

https://github.com/llvm/llvm-project/pull/96002