[llvm] [RISCV] Mark all registers marked isConstant as reserved (PR #96002)

[Craig Topper via llvm-commits]

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@@ -104,14 +104,16 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
-  // Mark any registers requested to be reserved as such
   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
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topperc wrote:

To be honest, I like your first patch better. As long as RISCVSubtarget uses `std::bitset<RISCV::NUM_TARGET_REGS>` to track reserved registers, we should continue iterating all of the registers.

https://github.com/llvm/llvm-project/pull/96002