[llvm] [RISCV] Introduce the RISCVLoopIdiomRecognizePass (PR #92441)

[Petr Penzin via llvm-commits]

ppenzin wrote:

> As a starting point, have you considered simply generalizing the aarch64 pass into a shared pass which can run on both targets? This would get you code generation via masked.loads for this case - but not the VP & VL predicated form.

I think it makes sense to have a pass separate from AArch64, the semantics of SVE and RVV are different enough that these passes are bound to diverge at some point.

https://github.com/llvm/llvm-project/pull/92441