[llvm] [RISCV] Introduce the RISCVLoopIdiomRecognizePass (PR #92441)

[Craig Topper via llvm-commits]

topperc wrote:

> > As a starting point, have you considered simply generalizing the aarch64 pass into a shared pass which can run on both targets? This would get you code generation via masked.loads for this case - but not the VP & VL predicated form.
> 
> I think it makes sense to have a pass separate from AArch64, the semantics of SVE and RVV are different enough that these passes are bound to diverge at some point.

All of the idiom detection code is currently identical. There are some minor differences that I think came from the timing of when we copied the code and later changes made by AArch64. It was not intended for them to diverge. This is one problem having a single pass solves.

There are differences in how we expand the code. Maybe we can use the TTI hooks the middle loop vectorizer uses to have different strategies for AArch64 and RISC-V. If that gets too complicated we could have a common base class that AArch64 and RISC-V both inherit their own passes from so they can share the code that makes sense.

https://github.com/llvm/llvm-project/pull/92441