[llvm] [AArch64][GlobalISel] Push ADD/SUB through Extend Instructions (PR #90964)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 22 06:44:42 PDT 2024
https://github.com/chuongg3 updated https://github.com/llvm/llvm-project/pull/90964
>From acb4786582f97668b0bbf03440b464e6b907c19b Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Thu, 2 May 2024 13:32:36 +0000
Subject: [PATCH 1/2] [AArch64][GlobalISel] Pre-commit test for Push ADD/SUB
through {S|Z}EXT
---
.../AArch64/GlobalISel/combine-add.mir | 119 ++++++
llvm/test/CodeGen/AArch64/arm64-vadd.ll | 396 ++++++++++++++++++
2 files changed, 515 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
index fad3655da9d01..78411f34bebd3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
@@ -207,3 +207,122 @@ body: |
%3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)
$q0 = COPY %3(<4 x s32>)
...
+---
+name: saddl_v8i8_v8i32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: saddl_v8i8_v8i32
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[SEXT]], [[SEXT1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
+ %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
+ %4:_(<8 x s32>) = G_ADD %2, %3
+ %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
+ $q0 = COPY %5(<4 x s32>)
+ $q1 = COPY %6(<4 x s32>)
+ RET_ReallyLR implicit $q0, implicit $q1
+...
+
+---
+name: uaddl_v8i8_v8i32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: uaddl_v8i8_v8i32
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[ZEXT]], [[ZEXT1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
+ %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
+ %4:_(<8 x s32>) = G_ADD %2, %3
+ %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
+ $q0 = COPY %5(<4 x s32>)
+ $q1 = COPY %6(<4 x s32>)
+ RET_ReallyLR implicit $q0, implicit $q1
+...
+
+---
+name: ssubl_v8i8_v8i32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: ssubl_v8i8_v8i32
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[SEXT]], [[SEXT1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SUB]](<8 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
+ %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
+ %4:_(<8 x s32>) = G_SUB %2, %3
+ %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
+ $q0 = COPY %5(<4 x s32>)
+ $q1 = COPY %6(<4 x s32>)
+ RET_ReallyLR implicit $q0, implicit $q1
+...
+
+---
+name: usubl_v8i8_v8i32
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1
+
+ ; CHECK-LABEL: name: usubl_v8i8_v8i32
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[ZEXT]], [[ZEXT1]]
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SUB]](<8 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
+ ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
+ %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
+ %4:_(<8 x s32>) = G_SUB %2, %3
+ %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
+ $q0 = COPY %5(<4 x s32>)
+ $q1 = COPY %6(<4 x s32>)
+ RET_ReallyLR implicit $q0, implicit $q1
+...
diff --git a/llvm/test/CodeGen/AArch64/arm64-vadd.ll b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
index 38a568ac91916..781ea4b82302c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
@@ -1193,6 +1193,402 @@ define <2 x i64> @ssubl2_duplhs(i32 %lhs, <4 x i32> %rhs) {
ret <2 x i64> %res
}
+define <8 x i32> @saddl_v8i8_v8i32(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-SD-LABEL: saddl_v8i8_v8i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: saddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll2 v1.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: saddl_v8i8_v8i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: saddl v0.4s, v2.4h, v1.4h
+; CHECK-GI-NEXT: saddl2 v1.4s, v2.8h, v1.8h
+; CHECK-GI-NEXT: ret
+ %c = sext <8 x i8> %a to <8 x i32>
+ %d = sext <8 x i8> %b to <8 x i32>
+ %e = add <8 x i32> %c, %d
+ ret <8 x i32> %e
+}
+
+define <8 x i64> @saddl_v8i8_v8i64(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-SD-LABEL: saddl_v8i8_v8i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: saddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll v0.2d, v1.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v1.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: saddl_v8i8_v8i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: saddl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: saddl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: saddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
+ %c = sext <8 x i8> %a to <8 x i64>
+ %d = sext <8 x i8> %b to <8 x i64>
+ %e = add <8 x i64> %c, %d
+ ret <8 x i64> %e
+}
+
+define <8 x i64> @saddl_v8i16_v8i64(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-SD-LABEL: saddl_v8i16_v8i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: saddl v2.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: saddl2 v4.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: sshll v0.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v4.4s, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v4.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: saddl_v8i16_v8i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: saddl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: saddl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: saddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
+ %c = sext <8 x i16> %a to <8 x i64>
+ %d = sext <8 x i16> %b to <8 x i64>
+ %e = add <8 x i64> %c, %d
+ ret <8 x i64> %e
+}
+
+define <16 x i32> @saddl_v16i8_v16i32(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: saddl_v16i8_v16i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: saddl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: saddl2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: saddl_v16i8_v16i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v4.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll2 v5.8h, v1.16b, #0
+; CHECK-GI-NEXT: saddl v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: saddl2 v1.4s, v2.8h, v3.8h
+; CHECK-GI-NEXT: saddl v2.4s, v4.4h, v5.4h
+; CHECK-GI-NEXT: saddl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: ret
+ %c = sext <16 x i8> %a to <16 x i32>
+ %d = sext <16 x i8> %b to <16 x i32>
+ %e = add <16 x i32> %c, %d
+ ret <16 x i32> %e
+}
+
+define <16 x i64> @saddl_v16i8_v16i64(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: saddl_v16i8_v16i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: saddl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: saddl2 v0.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: sshll v3.4s, v2.4h, #0
+; CHECK-SD-NEXT: sshll2 v2.4s, v2.8h, #0
+; CHECK-SD-NEXT: sshll v5.4s, v0.4h, #0
+; CHECK-SD-NEXT: sshll2 v6.4s, v0.8h, #0
+; CHECK-SD-NEXT: sshll2 v1.2d, v3.4s, #0
+; CHECK-SD-NEXT: sshll v0.2d, v3.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: sshll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: sshll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: sshll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: saddl_v16i8_v16i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: sshll2 v1.8h, v1.16b, #0
+; CHECK-GI-NEXT: sshll v4.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll v2.4s, v3.4h, #0
+; CHECK-GI-NEXT: sshll v6.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v3.4s, v3.8h, #0
+; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v16.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll2 v17.4s, v1.8h, #0
+; CHECK-GI-NEXT: saddl v0.2d, v4.2s, v2.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v4.4s, v2.4s
+; CHECK-GI-NEXT: saddl v2.2d, v5.2s, v3.2s
+; CHECK-GI-NEXT: saddl2 v3.2d, v5.4s, v3.4s
+; CHECK-GI-NEXT: saddl v4.2d, v6.2s, v7.2s
+; CHECK-GI-NEXT: saddl2 v5.2d, v6.4s, v7.4s
+; CHECK-GI-NEXT: saddl v6.2d, v16.2s, v17.2s
+; CHECK-GI-NEXT: saddl2 v7.2d, v16.4s, v17.4s
+; CHECK-GI-NEXT: ret
+ %c = sext <16 x i8> %a to <16 x i64>
+ %d = sext <16 x i8> %b to <16 x i64>
+ %e = add <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <16 x i64> @saddl_v16i16_v16i64(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-SD-LABEL: saddl_v16i16_v16i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: saddl v5.4s, v1.4h, v3.4h
+; CHECK-SD-NEXT: saddl v4.4s, v0.4h, v2.4h
+; CHECK-SD-NEXT: saddl2 v2.4s, v0.8h, v2.8h
+; CHECK-SD-NEXT: saddl2 v6.4s, v1.8h, v3.8h
+; CHECK-SD-NEXT: sshll2 v1.2d, v4.4s, #0
+; CHECK-SD-NEXT: sshll v0.2d, v4.2s, #0
+; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: sshll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: sshll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: sshll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: saddl_v16i16_v16i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v4.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll v6.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v16.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll v17.4s, v3.4h, #0
+; CHECK-GI-NEXT: sshll2 v18.4s, v1.8h, #0
+; CHECK-GI-NEXT: sshll2 v19.4s, v3.8h, #0
+; CHECK-GI-NEXT: saddl v0.2d, v4.2s, v6.2s
+; CHECK-GI-NEXT: saddl2 v1.2d, v4.4s, v6.4s
+; CHECK-GI-NEXT: saddl v2.2d, v5.2s, v16.2s
+; CHECK-GI-NEXT: saddl2 v3.2d, v5.4s, v16.4s
+; CHECK-GI-NEXT: saddl v4.2d, v7.2s, v17.2s
+; CHECK-GI-NEXT: saddl2 v5.2d, v7.4s, v17.4s
+; CHECK-GI-NEXT: saddl v6.2d, v18.2s, v19.2s
+; CHECK-GI-NEXT: saddl2 v7.2d, v18.4s, v19.4s
+; CHECK-GI-NEXT: ret
+ %c = sext <16 x i16> %a to <16 x i64>
+ %d = sext <16 x i16> %b to <16 x i64>
+ %e = add <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <8 x i32> @uaddl_v8i8_v8i32(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-SD-LABEL: uaddl_v8i8_v8i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uaddl_v8i8_v8i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: uaddl v0.4s, v2.4h, v1.4h
+; CHECK-GI-NEXT: uaddl2 v1.4s, v2.8h, v1.8h
+; CHECK-GI-NEXT: ret
+ %c = zext <8 x i8> %a to <8 x i32>
+ %d = zext <8 x i8> %b to <8 x i32>
+ %e = add <8 x i32> %c, %d
+ ret <8 x i32> %e
+}
+
+define <8 x i64> @uaddl_v8i8_v8i64(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-SD-LABEL: uaddl_v8i8_v8i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0
+; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0
+; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uaddl_v8i8_v8i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: uaddl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: uaddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
+ %c = zext <8 x i8> %a to <8 x i64>
+ %d = zext <8 x i8> %b to <8 x i64>
+ %e = add <8 x i64> %c, %d
+ ret <8 x i64> %e
+}
+
+define <8 x i64> @uaddl_v8i16_v8i64(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-SD-LABEL: uaddl_v8i16_v8i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uaddl v2.4s, v0.4h, v1.4h
+; CHECK-SD-NEXT: uaddl2 v4.4s, v0.8h, v1.8h
+; CHECK-SD-NEXT: ushll v0.2d, v2.2s, #0
+; CHECK-SD-NEXT: ushll2 v3.2d, v4.4s, #0
+; CHECK-SD-NEXT: ushll2 v1.2d, v2.4s, #0
+; CHECK-SD-NEXT: ushll v2.2d, v4.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uaddl_v8i16_v8i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v4.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v2.2s, v3.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v2.4s, v3.4s
+; CHECK-GI-NEXT: uaddl v2.2d, v4.2s, v5.2s
+; CHECK-GI-NEXT: uaddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: ret
+ %c = zext <8 x i16> %a to <8 x i64>
+ %d = zext <8 x i16> %b to <8 x i64>
+ %e = add <8 x i64> %c, %d
+ ret <8 x i64> %e
+}
+
+define <16 x i32> @uaddl_v16i8_v16i32(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: uaddl_v16i8_v16i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uaddl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: uaddl2 v4.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: ushll v0.4s, v2.4h, #0
+; CHECK-SD-NEXT: ushll2 v3.4s, v4.8h, #0
+; CHECK-SD-NEXT: ushll2 v1.4s, v2.8h, #0
+; CHECK-SD-NEXT: ushll v2.4s, v4.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uaddl_v16i8_v16i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll2 v4.8h, v0.16b, #0
+; CHECK-GI-NEXT: ushll2 v5.8h, v1.16b, #0
+; CHECK-GI-NEXT: uaddl v0.4s, v2.4h, v3.4h
+; CHECK-GI-NEXT: uaddl2 v1.4s, v2.8h, v3.8h
+; CHECK-GI-NEXT: uaddl v2.4s, v4.4h, v5.4h
+; CHECK-GI-NEXT: uaddl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: ret
+ %c = zext <16 x i8> %a to <16 x i32>
+ %d = zext <16 x i8> %b to <16 x i32>
+ %e = add <16 x i32> %c, %d
+ ret <16 x i32> %e
+}
+
+define <16 x i64> @uaddl_v16i8_v16i64(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: uaddl_v16i8_v16i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uaddl v2.8h, v0.8b, v1.8b
+; CHECK-SD-NEXT: uaddl2 v0.8h, v0.16b, v1.16b
+; CHECK-SD-NEXT: ushll v3.4s, v2.4h, #0
+; CHECK-SD-NEXT: ushll2 v2.4s, v2.8h, #0
+; CHECK-SD-NEXT: ushll v5.4s, v0.4h, #0
+; CHECK-SD-NEXT: ushll2 v6.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll2 v1.2d, v3.4s, #0
+; CHECK-SD-NEXT: ushll v0.2d, v3.2s, #0
+; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ushll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: ushll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: ushll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uaddl_v16i8_v16i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
+; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-GI-NEXT: ushll2 v1.8h, v1.16b, #0
+; CHECK-GI-NEXT: ushll v4.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #0
+; CHECK-GI-NEXT: ushll v6.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #0
+; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v16.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll2 v17.4s, v1.8h, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v4.2s, v2.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v4.4s, v2.4s
+; CHECK-GI-NEXT: uaddl v2.2d, v5.2s, v3.2s
+; CHECK-GI-NEXT: uaddl2 v3.2d, v5.4s, v3.4s
+; CHECK-GI-NEXT: uaddl v4.2d, v6.2s, v7.2s
+; CHECK-GI-NEXT: uaddl2 v5.2d, v6.4s, v7.4s
+; CHECK-GI-NEXT: uaddl v6.2d, v16.2s, v17.2s
+; CHECK-GI-NEXT: uaddl2 v7.2d, v16.4s, v17.4s
+; CHECK-GI-NEXT: ret
+ %c = zext <16 x i8> %a to <16 x i64>
+ %d = zext <16 x i8> %b to <16 x i64>
+ %e = add <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
+define <16 x i64> @uaddl_v16i16_v16i64(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-SD-LABEL: uaddl_v16i16_v16i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uaddl v5.4s, v1.4h, v3.4h
+; CHECK-SD-NEXT: uaddl v4.4s, v0.4h, v2.4h
+; CHECK-SD-NEXT: uaddl2 v2.4s, v0.8h, v2.8h
+; CHECK-SD-NEXT: uaddl2 v6.4s, v1.8h, v3.8h
+; CHECK-SD-NEXT: ushll2 v1.2d, v4.4s, #0
+; CHECK-SD-NEXT: ushll v0.2d, v4.2s, #0
+; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0
+; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0
+; CHECK-SD-NEXT: ushll v4.2d, v5.2s, #0
+; CHECK-SD-NEXT: ushll2 v7.2d, v6.4s, #0
+; CHECK-SD-NEXT: ushll2 v5.2d, v5.4s, #0
+; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uaddl_v16i16_v16i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v4.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v5.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll v6.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v16.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll v17.4s, v3.4h, #0
+; CHECK-GI-NEXT: ushll2 v18.4s, v1.8h, #0
+; CHECK-GI-NEXT: ushll2 v19.4s, v3.8h, #0
+; CHECK-GI-NEXT: uaddl v0.2d, v4.2s, v6.2s
+; CHECK-GI-NEXT: uaddl2 v1.2d, v4.4s, v6.4s
+; CHECK-GI-NEXT: uaddl v2.2d, v5.2s, v16.2s
+; CHECK-GI-NEXT: uaddl2 v3.2d, v5.4s, v16.4s
+; CHECK-GI-NEXT: uaddl v4.2d, v7.2s, v17.2s
+; CHECK-GI-NEXT: uaddl2 v5.2d, v7.4s, v17.4s
+; CHECK-GI-NEXT: uaddl v6.2d, v18.2s, v19.2s
+; CHECK-GI-NEXT: uaddl2 v7.2d, v18.4s, v19.4s
+; CHECK-GI-NEXT: ret
+ %c = zext <16 x i16> %a to <16 x i64>
+ %d = zext <16 x i16> %b to <16 x i64>
+ %e = add <16 x i64> %c, %d
+ ret <16 x i64> %e
+}
+
define <8 x i8> @addhn8b_natural(ptr %A, ptr %B) nounwind {
; CHECK-SD-LABEL: addhn8b_natural:
; CHECK-SD: // %bb.0:
>From 30eb02d26dbdec2a5a2d550c29c5c29dc3331979 Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Thu, 2 May 2024 12:56:06 +0000
Subject: [PATCH 2/2] [AArch64][GlobalISel] Push ADD/SUB through {S|Z}EXT
i32 add(i32 ext i8, i32 ext i8) =>
i32 ext(i16 add(i16 ext i8, i16 ext i8))
Reduces the amount of shift instructions generated by selecting
{s|u}addl instruction as early as possible
During instruction selection the result will be selected as:
i32 ext (i16 uaddl i8, i8)
Instead of:
i32 uaddl (i16 ext i8, i16 ext i8)
---
llvm/lib/Target/AArch64/AArch64Combine.td | 19 +-
.../GISel/AArch64PreLegalizerCombiner.cpp | 49 ++++
.../AArch64/GlobalISel/combine-add.mir | 36 +--
llvm/test/CodeGen/AArch64/aarch64-addv.ll | 25 +-
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 82 ++++---
llvm/test/CodeGen/AArch64/arm64-vadd.ll | 228 ++++++++----------
llvm/test/CodeGen/AArch64/vecreduce-add.ll | 142 ++++++-----
7 files changed, 313 insertions(+), 268 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 10cad6d192440..a387c12863094 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -52,6 +52,19 @@ def ext_uaddv_to_uaddlv : GICombineRule<
(apply [{ applyExtUaddvToUaddlv(*${root}, MRI, B, Observer, ${matchinfo}); }])
>;
+class push_opcode_through_ext<Instruction opcode, Instruction extOpcode> : GICombineRule <
+ (defs root:$root),
+ (match (extOpcode $ext1, $src1):$ExtMI,
+ (extOpcode $ext2, $src2),
+ (opcode $dst, $ext1, $ext2):$root,
+ [{ return matchPushAddSubExt(*${root}, MRI, ${dst}.getReg(), ${src1}.getReg(), ${src2}.getReg()); }]),
+ (apply [{ applyPushAddSubExt(*${root}, MRI, B, ${ExtMI}->getOpcode() == TargetOpcode::G_SEXT, ${dst}.getReg(), ${src1}.getReg(), ${src2}.getReg()); }])>;
+
+def push_sub_through_zext : push_opcode_through_ext<G_SUB, G_ZEXT>;
+def push_add_through_zext : push_opcode_through_ext<G_ADD, G_ZEXT>;
+def push_sub_through_sext : push_opcode_through_ext<G_SUB, G_SEXT>;
+def push_add_through_sext : push_opcode_through_ext<G_ADD, G_SEXT>;
+
def AArch64PreLegalizerCombiner: GICombiner<
"AArch64PreLegalizerCombinerImpl", [all_combines,
fconstant_to_constant,
@@ -59,7 +72,11 @@ def AArch64PreLegalizerCombiner: GICombiner<
fold_global_offset,
shuffle_to_extract,
ext_addv_to_udot_addv,
- ext_uaddv_to_uaddlv]> {
+ ext_uaddv_to_uaddlv,
+ push_sub_through_zext,
+ push_add_through_zext,
+ push_sub_through_sext,
+ push_add_through_sext]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index a82d3cd095659..90b64c416b444 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -554,6 +554,55 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
MI.eraseFromParent();
}
+// Pushes ADD/SUB through extend instructions to decrease the number of extend
+// instruction at the end by allowing selection of {s|u}addl sooner
+
+// i32 add(i32 ext i8, i32 ext i8) => i32 ext(i16 add(i16 ext i8, i16 ext i8))
+bool matchPushAddSubExt(MachineInstr &MI, MachineRegisterInfo &MRI,
+ Register DstReg, Register SrcReg1, Register SrcReg2) {
+ assert(MI.getOpcode() == TargetOpcode::G_ADD ||
+ MI.getOpcode() == TargetOpcode::G_SUB &&
+ "Expected a G_ADD or G_SUB instruction\n");
+
+ // Deal with vector types only
+ LLT DstTy = MRI.getType(DstReg);
+ if (!DstTy.isVector())
+ return false;
+
+ // Return true if G_{S|Z}EXT instruction is more than 2* source
+ Register ExtDstReg = MI.getOperand(1).getReg();
+ LLT ExtDstTy = MRI.getType(ExtDstReg);
+ LLT Ext1SrcTy = MRI.getType(SrcReg1);
+ LLT Ext2SrcTy = MRI.getType(SrcReg2);
+ if (((Ext1SrcTy.getScalarSizeInBits() == 8 &&
+ ExtDstTy.getScalarSizeInBits() == 32) ||
+ ((Ext1SrcTy.getScalarSizeInBits() == 8 ||
+ Ext1SrcTy.getScalarSizeInBits() == 16) &&
+ ExtDstTy.getScalarSizeInBits() == 64)) &&
+ Ext1SrcTy == Ext2SrcTy)
+ return true;
+
+ return false;
+}
+
+void applyPushAddSubExt(MachineInstr &MI, MachineRegisterInfo &MRI,
+ MachineIRBuilder &B, bool isSExt, Register DstReg,
+ Register SrcReg1, Register SrcReg2) {
+ LLT SrcTy = MRI.getType(SrcReg1);
+ LLT MidTy = SrcTy.changeElementSize(SrcTy.getScalarSizeInBits() * 2);
+ unsigned Opc = isSExt ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
+ Register Ext1Reg = B.buildInstr(Opc, {MidTy}, {SrcReg1}).getReg(0);
+ Register Ext2Reg = B.buildInstr(Opc, {MidTy}, {SrcReg2}).getReg(0);
+ Register AddReg =
+ B.buildInstr(MI.getOpcode(), {MidTy}, {Ext1Reg, Ext2Reg}).getReg(0);
+ if (MI.getOpcode() == TargetOpcode::G_ADD)
+ B.buildInstr(Opc, {DstReg}, {AddReg});
+ else
+ B.buildSExt(DstReg, AddReg);
+
+ MI.eraseFromParent();
+}
+
bool tryToSimplifyUADDO(MachineInstr &MI, MachineIRBuilder &B,
CombinerHelper &Helper, GISelChangeObserver &Observer) {
// Try simplify G_UADDO with 8 or 16 bit operands to wide G_ADD and TBNZ if
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
index 78411f34bebd3..a0142afd06777 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
@@ -219,10 +219,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY]](<8 x s8>)
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY1]](<8 x s8>)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[SEXT]], [[SEXT1]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[SEXT]], [[SEXT1]]
+ ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[ADD]](<8 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT2]](<8 x s32>)
; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
@@ -249,10 +250,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY]](<8 x s8>)
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY1]](<8 x s8>)
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[ZEXT]], [[ZEXT1]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[ZEXT1]]
+ ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[ADD]](<8 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ZEXT2]](<8 x s32>)
; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
@@ -279,10 +281,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY]](<8 x s8>)
- ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY1]](<8 x s8>)
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[SEXT]], [[SEXT1]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SUB]](<8 x s32>)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[SEXT]], [[SEXT1]]
+ ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[SUB]](<8 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT2]](<8 x s32>)
; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
@@ -309,10 +312,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY]](<8 x s8>)
- ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY1]](<8 x s8>)
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[ZEXT]], [[ZEXT1]]
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SUB]](<8 x s32>)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[ZEXT]], [[ZEXT1]]
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[SUB]](<8 x s16>)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT]](<8 x s32>)
; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
diff --git a/llvm/test/CodeGen/AArch64/aarch64-addv.ll b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
index 94b792b887eb4..def4192b0e005 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-addv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
@@ -94,18 +94,19 @@ define i32 @oversized_ADDV_256(ptr noalias nocapture readonly %arg1, ptr noalias
;
; GISEL-LABEL: oversized_ADDV_256:
; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: ldr d0, [x0]
-; GISEL-NEXT: ldr d1, [x1]
-; GISEL-NEXT: ushll v0.8h, v0.8b, #0
-; GISEL-NEXT: ushll v1.8h, v1.8b, #0
-; GISEL-NEXT: usubl v2.4s, v0.4h, v1.4h
-; GISEL-NEXT: usubl2 v0.4s, v0.8h, v1.8h
-; GISEL-NEXT: cmlt v1.4s, v2.4s, #0
-; GISEL-NEXT: cmlt v3.4s, v0.4s, #0
-; GISEL-NEXT: neg v4.4s, v2.4s
-; GISEL-NEXT: neg v5.4s, v0.4s
-; GISEL-NEXT: bsl v1.16b, v4.16b, v2.16b
-; GISEL-NEXT: bit v0.16b, v5.16b, v3.16b
+; GISEL-NEXT: ldr d1, [x0]
+; GISEL-NEXT: ldr d2, [x1]
+; GISEL-NEXT: movi v0.2d, #0000000000000000
+; GISEL-NEXT: usubl v1.8h, v1.8b, v2.8b
+; GISEL-NEXT: sshll v2.4s, v1.4h, #0
+; GISEL-NEXT: sshll2 v3.4s, v1.8h, #0
+; GISEL-NEXT: ssubw2 v0.4s, v0.4s, v1.8h
+; GISEL-NEXT: cmlt v4.4s, v2.4s, #0
+; GISEL-NEXT: cmlt v5.4s, v3.4s, #0
+; GISEL-NEXT: neg v6.4s, v2.4s
+; GISEL-NEXT: mov v1.16b, v4.16b
+; GISEL-NEXT: bif v0.16b, v3.16b, v5.16b
+; GISEL-NEXT: bsl v1.16b, v6.16b, v2.16b
; GISEL-NEXT: add v0.4s, v1.4s, v0.4s
; GISEL-NEXT: addv s0, v0.4s
; GISEL-NEXT: fmov w0, s0
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index f7d31a214563b..178c229d04e47 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -289,26 +289,27 @@ define i32 @uabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: uabd16b_rdx_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll.8h v2, v0, #0
-; CHECK-GI-NEXT: ushll.8h v3, v1, #0
-; CHECK-GI-NEXT: ushll2.8h v0, v0, #0
-; CHECK-GI-NEXT: ushll2.8h v1, v1, #0
-; CHECK-GI-NEXT: usubl.4s v4, v2, v3
-; CHECK-GI-NEXT: usubl2.4s v2, v2, v3
-; CHECK-GI-NEXT: usubl.4s v3, v0, v1
-; CHECK-GI-NEXT: usubl2.4s v0, v0, v1
-; CHECK-GI-NEXT: cmlt.4s v1, v4, #0
-; CHECK-GI-NEXT: cmlt.4s v5, v2, #0
-; CHECK-GI-NEXT: neg.4s v16, v4
-; CHECK-GI-NEXT: cmlt.4s v6, v3, #0
-; CHECK-GI-NEXT: cmlt.4s v7, v0, #0
-; CHECK-GI-NEXT: neg.4s v17, v2
-; CHECK-GI-NEXT: neg.4s v18, v3
-; CHECK-GI-NEXT: neg.4s v19, v0
-; CHECK-GI-NEXT: bsl.16b v1, v16, v4
-; CHECK-GI-NEXT: bit.16b v2, v17, v5
-; CHECK-GI-NEXT: bit.16b v3, v18, v6
-; CHECK-GI-NEXT: bit.16b v0, v19, v7
+; CHECK-GI-NEXT: usubl.8h v3, v0, v1
+; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
+; CHECK-GI-NEXT: usubl2.8h v0, v0, v1
+; CHECK-GI-NEXT: sshll.4s v1, v3, #0
+; CHECK-GI-NEXT: sshll2.4s v4, v3, #0
+; CHECK-GI-NEXT: sshll.4s v5, v0, #0
+; CHECK-GI-NEXT: sshll2.4s v6, v0, #0
+; CHECK-GI-NEXT: ssubw2.4s v3, v2, v3
+; CHECK-GI-NEXT: ssubw2.4s v0, v2, v0
+; CHECK-GI-NEXT: cmlt.4s v2, v1, #0
+; CHECK-GI-NEXT: cmlt.4s v7, v4, #0
+; CHECK-GI-NEXT: neg.4s v16, v1
+; CHECK-GI-NEXT: cmlt.4s v17, v5, #0
+; CHECK-GI-NEXT: cmlt.4s v18, v6, #0
+; CHECK-GI-NEXT: neg.4s v19, v5
+; CHECK-GI-NEXT: bit.16b v1, v16, v2
+; CHECK-GI-NEXT: mov.16b v2, v7
+; CHECK-GI-NEXT: bif.16b v0, v6, v18
+; CHECK-GI-NEXT: bsl.16b v2, v3, v4
+; CHECK-GI-NEXT: mov.16b v3, v17
+; CHECK-GI-NEXT: bsl.16b v3, v19, v5
; CHECK-GI-NEXT: add.4s v1, v1, v2
; CHECK-GI-NEXT: add.4s v0, v3, v0
; CHECK-GI-NEXT: add.4s v0, v1, v0
@@ -336,26 +337,27 @@ define i32 @sabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: sabd16b_rdx_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll.8h v2, v0, #0
-; CHECK-GI-NEXT: sshll.8h v3, v1, #0
-; CHECK-GI-NEXT: sshll2.8h v0, v0, #0
-; CHECK-GI-NEXT: sshll2.8h v1, v1, #0
-; CHECK-GI-NEXT: ssubl.4s v4, v2, v3
-; CHECK-GI-NEXT: ssubl2.4s v2, v2, v3
-; CHECK-GI-NEXT: ssubl.4s v3, v0, v1
-; CHECK-GI-NEXT: ssubl2.4s v0, v0, v1
-; CHECK-GI-NEXT: cmlt.4s v1, v4, #0
-; CHECK-GI-NEXT: cmlt.4s v5, v2, #0
-; CHECK-GI-NEXT: neg.4s v16, v4
-; CHECK-GI-NEXT: cmlt.4s v6, v3, #0
-; CHECK-GI-NEXT: cmlt.4s v7, v0, #0
-; CHECK-GI-NEXT: neg.4s v17, v2
-; CHECK-GI-NEXT: neg.4s v18, v3
-; CHECK-GI-NEXT: neg.4s v19, v0
-; CHECK-GI-NEXT: bsl.16b v1, v16, v4
-; CHECK-GI-NEXT: bit.16b v2, v17, v5
-; CHECK-GI-NEXT: bit.16b v3, v18, v6
-; CHECK-GI-NEXT: bit.16b v0, v19, v7
+; CHECK-GI-NEXT: ssubl.8h v3, v0, v1
+; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
+; CHECK-GI-NEXT: ssubl2.8h v0, v0, v1
+; CHECK-GI-NEXT: sshll.4s v1, v3, #0
+; CHECK-GI-NEXT: sshll2.4s v4, v3, #0
+; CHECK-GI-NEXT: sshll.4s v5, v0, #0
+; CHECK-GI-NEXT: sshll2.4s v6, v0, #0
+; CHECK-GI-NEXT: ssubw2.4s v3, v2, v3
+; CHECK-GI-NEXT: ssubw2.4s v0, v2, v0
+; CHECK-GI-NEXT: cmlt.4s v2, v1, #0
+; CHECK-GI-NEXT: cmlt.4s v7, v4, #0
+; CHECK-GI-NEXT: neg.4s v16, v1
+; CHECK-GI-NEXT: cmlt.4s v17, v5, #0
+; CHECK-GI-NEXT: cmlt.4s v18, v6, #0
+; CHECK-GI-NEXT: neg.4s v19, v5
+; CHECK-GI-NEXT: bit.16b v1, v16, v2
+; CHECK-GI-NEXT: mov.16b v2, v7
+; CHECK-GI-NEXT: bif.16b v0, v6, v18
+; CHECK-GI-NEXT: bsl.16b v2, v3, v4
+; CHECK-GI-NEXT: mov.16b v3, v17
+; CHECK-GI-NEXT: bsl.16b v3, v19, v5
; CHECK-GI-NEXT: add.4s v1, v1, v2
; CHECK-GI-NEXT: add.4s v0, v3, v0
; CHECK-GI-NEXT: add.4s v0, v1, v0
diff --git a/llvm/test/CodeGen/AArch64/arm64-vadd.ll b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
index 781ea4b82302c..044c60500ff65 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
@@ -1203,10 +1203,9 @@ define <8 x i32> @saddl_v8i8_v8i32(<8 x i8> %a, <8 x i8> %b) {
;
; CHECK-GI-LABEL: saddl_v8i8_v8i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
-; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
-; CHECK-GI-NEXT: saddl v0.4s, v2.4h, v1.4h
-; CHECK-GI-NEXT: saddl2 v1.4s, v2.8h, v1.8h
+; CHECK-GI-NEXT: saddl v1.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: sshll v0.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v1.4s, v1.8h, #0
; CHECK-GI-NEXT: ret
%c = sext <8 x i8> %a to <8 x i32>
%d = sext <8 x i8> %b to <8 x i32>
@@ -1228,16 +1227,13 @@ define <8 x i64> @saddl_v8i8_v8i64(<8 x i8> %a, <8 x i8> %b) {
;
; CHECK-GI-LABEL: saddl_v8i8_v8i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
-; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
-; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
-; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0
-; CHECK-GI-NEXT: sshll2 v5.4s, v1.8h, #0
-; CHECK-GI-NEXT: saddl v0.2d, v2.2s, v3.2s
-; CHECK-GI-NEXT: saddl2 v1.2d, v2.4s, v3.4s
-; CHECK-GI-NEXT: saddl v2.2d, v4.2s, v5.2s
-; CHECK-GI-NEXT: saddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: saddl v0.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: sshll v1.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v3.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll v0.2d, v1.2s, #0
+; CHECK-GI-NEXT: sshll2 v1.2d, v1.4s, #0
+; CHECK-GI-NEXT: sshll v2.2d, v3.2s, #0
+; CHECK-GI-NEXT: sshll2 v3.2d, v3.4s, #0
; CHECK-GI-NEXT: ret
%c = sext <8 x i8> %a to <8 x i64>
%d = sext <8 x i8> %b to <8 x i64>
@@ -1258,14 +1254,12 @@ define <8 x i64> @saddl_v8i16_v8i64(<8 x i16> %a, <8 x i16> %b) {
;
; CHECK-GI-LABEL: saddl_v8i16_v8i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0
-; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
-; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0
-; CHECK-GI-NEXT: sshll2 v5.4s, v1.8h, #0
-; CHECK-GI-NEXT: saddl v0.2d, v2.2s, v3.2s
-; CHECK-GI-NEXT: saddl2 v1.2d, v2.4s, v3.4s
-; CHECK-GI-NEXT: saddl v2.2d, v4.2s, v5.2s
-; CHECK-GI-NEXT: saddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: saddl v2.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: saddl2 v3.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT: sshll v0.2d, v2.2s, #0
+; CHECK-GI-NEXT: sshll2 v1.2d, v2.4s, #0
+; CHECK-GI-NEXT: sshll v2.2d, v3.2s, #0
+; CHECK-GI-NEXT: sshll2 v3.2d, v3.4s, #0
; CHECK-GI-NEXT: ret
%c = sext <8 x i16> %a to <8 x i64>
%d = sext <8 x i16> %b to <8 x i64>
@@ -1286,14 +1280,12 @@ define <16 x i32> @saddl_v16i8_v16i32(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: saddl_v16i8_v16i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
-; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
-; CHECK-GI-NEXT: sshll2 v4.8h, v0.16b, #0
-; CHECK-GI-NEXT: sshll2 v5.8h, v1.16b, #0
-; CHECK-GI-NEXT: saddl v0.4s, v2.4h, v3.4h
-; CHECK-GI-NEXT: saddl2 v1.4s, v2.8h, v3.8h
-; CHECK-GI-NEXT: saddl v2.4s, v4.4h, v5.4h
-; CHECK-GI-NEXT: saddl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: saddl v2.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: saddl2 v3.8h, v0.16b, v1.16b
+; CHECK-GI-NEXT: sshll v0.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll2 v1.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll v2.4s, v3.4h, #0
+; CHECK-GI-NEXT: sshll2 v3.4s, v3.8h, #0
; CHECK-GI-NEXT: ret
%c = sext <16 x i8> %a to <16 x i32>
%d = sext <16 x i8> %b to <16 x i32>
@@ -1322,26 +1314,20 @@ define <16 x i64> @saddl_v16i8_v16i64(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: saddl_v16i8_v16i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0
-; CHECK-GI-NEXT: sshll v3.8h, v1.8b, #0
-; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
-; CHECK-GI-NEXT: sshll2 v1.8h, v1.16b, #0
-; CHECK-GI-NEXT: sshll v4.4s, v2.4h, #0
-; CHECK-GI-NEXT: sshll2 v5.4s, v2.8h, #0
-; CHECK-GI-NEXT: sshll v2.4s, v3.4h, #0
-; CHECK-GI-NEXT: sshll v6.4s, v0.4h, #0
-; CHECK-GI-NEXT: sshll2 v3.4s, v3.8h, #0
-; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
-; CHECK-GI-NEXT: sshll2 v16.4s, v0.8h, #0
-; CHECK-GI-NEXT: sshll2 v17.4s, v1.8h, #0
-; CHECK-GI-NEXT: saddl v0.2d, v4.2s, v2.2s
-; CHECK-GI-NEXT: saddl2 v1.2d, v4.4s, v2.4s
-; CHECK-GI-NEXT: saddl v2.2d, v5.2s, v3.2s
-; CHECK-GI-NEXT: saddl2 v3.2d, v5.4s, v3.4s
-; CHECK-GI-NEXT: saddl v4.2d, v6.2s, v7.2s
-; CHECK-GI-NEXT: saddl2 v5.2d, v6.4s, v7.4s
-; CHECK-GI-NEXT: saddl v6.2d, v16.2s, v17.2s
-; CHECK-GI-NEXT: saddl2 v7.2d, v16.4s, v17.4s
+; CHECK-GI-NEXT: saddl v2.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: saddl2 v0.8h, v0.16b, v1.16b
+; CHECK-GI-NEXT: sshll v1.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll2 v3.4s, v2.8h, #0
+; CHECK-GI-NEXT: sshll v5.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v7.4s, v0.8h, #0
+; CHECK-GI-NEXT: sshll v0.2d, v1.2s, #0
+; CHECK-GI-NEXT: sshll2 v1.2d, v1.4s, #0
+; CHECK-GI-NEXT: sshll v2.2d, v3.2s, #0
+; CHECK-GI-NEXT: sshll2 v3.2d, v3.4s, #0
+; CHECK-GI-NEXT: sshll v4.2d, v5.2s, #0
+; CHECK-GI-NEXT: sshll2 v5.2d, v5.4s, #0
+; CHECK-GI-NEXT: sshll v6.2d, v7.2s, #0
+; CHECK-GI-NEXT: sshll2 v7.2d, v7.4s, #0
; CHECK-GI-NEXT: ret
%c = sext <16 x i8> %a to <16 x i64>
%d = sext <16 x i8> %b to <16 x i64>
@@ -1368,22 +1354,18 @@ define <16 x i64> @saddl_v16i16_v16i64(<16 x i16> %a, <16 x i16> %b) {
;
; CHECK-GI-LABEL: saddl_v16i16_v16i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll v4.4s, v0.4h, #0
-; CHECK-GI-NEXT: sshll2 v5.4s, v0.8h, #0
-; CHECK-GI-NEXT: sshll v6.4s, v2.4h, #0
-; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
-; CHECK-GI-NEXT: sshll2 v16.4s, v2.8h, #0
-; CHECK-GI-NEXT: sshll v17.4s, v3.4h, #0
-; CHECK-GI-NEXT: sshll2 v18.4s, v1.8h, #0
-; CHECK-GI-NEXT: sshll2 v19.4s, v3.8h, #0
-; CHECK-GI-NEXT: saddl v0.2d, v4.2s, v6.2s
-; CHECK-GI-NEXT: saddl2 v1.2d, v4.4s, v6.4s
-; CHECK-GI-NEXT: saddl v2.2d, v5.2s, v16.2s
-; CHECK-GI-NEXT: saddl2 v3.2d, v5.4s, v16.4s
-; CHECK-GI-NEXT: saddl v4.2d, v7.2s, v17.2s
-; CHECK-GI-NEXT: saddl2 v5.2d, v7.4s, v17.4s
-; CHECK-GI-NEXT: saddl v6.2d, v18.2s, v19.2s
-; CHECK-GI-NEXT: saddl2 v7.2d, v18.4s, v19.4s
+; CHECK-GI-NEXT: saddl v4.4s, v0.4h, v2.4h
+; CHECK-GI-NEXT: saddl2 v5.4s, v0.8h, v2.8h
+; CHECK-GI-NEXT: saddl v6.4s, v1.4h, v3.4h
+; CHECK-GI-NEXT: saddl2 v7.4s, v1.8h, v3.8h
+; CHECK-GI-NEXT: sshll v0.2d, v4.2s, #0
+; CHECK-GI-NEXT: sshll2 v1.2d, v4.4s, #0
+; CHECK-GI-NEXT: sshll v2.2d, v5.2s, #0
+; CHECK-GI-NEXT: sshll2 v3.2d, v5.4s, #0
+; CHECK-GI-NEXT: sshll v4.2d, v6.2s, #0
+; CHECK-GI-NEXT: sshll2 v5.2d, v6.4s, #0
+; CHECK-GI-NEXT: sshll v6.2d, v7.2s, #0
+; CHECK-GI-NEXT: sshll2 v7.2d, v7.4s, #0
; CHECK-GI-NEXT: ret
%c = sext <16 x i16> %a to <16 x i64>
%d = sext <16 x i16> %b to <16 x i64>
@@ -1401,10 +1383,9 @@ define <8 x i32> @uaddl_v8i8_v8i32(<8 x i8> %a, <8 x i8> %b) {
;
; CHECK-GI-LABEL: uaddl_v8i8_v8i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
-; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-GI-NEXT: uaddl v0.4s, v2.4h, v1.4h
-; CHECK-GI-NEXT: uaddl2 v1.4s, v2.8h, v1.8h
+; CHECK-GI-NEXT: uaddl v1.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0
+; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
; CHECK-GI-NEXT: ret
%c = zext <8 x i8> %a to <8 x i32>
%d = zext <8 x i8> %b to <8 x i32>
@@ -1426,16 +1407,13 @@ define <8 x i64> @uaddl_v8i8_v8i64(<8 x i8> %a, <8 x i8> %b) {
;
; CHECK-GI-LABEL: uaddl_v8i8_v8i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
-; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
-; CHECK-GI-NEXT: ushll2 v4.4s, v0.8h, #0
-; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0
-; CHECK-GI-NEXT: uaddl v0.2d, v2.2s, v3.2s
-; CHECK-GI-NEXT: uaddl2 v1.2d, v2.4s, v3.4s
-; CHECK-GI-NEXT: uaddl v2.2d, v4.2s, v5.2s
-; CHECK-GI-NEXT: uaddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: uaddl v0.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #0
+; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0
+; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0
+; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0
; CHECK-GI-NEXT: ret
%c = zext <8 x i8> %a to <8 x i64>
%d = zext <8 x i8> %b to <8 x i64>
@@ -1456,14 +1434,12 @@ define <8 x i64> @uaddl_v8i16_v8i64(<8 x i16> %a, <8 x i16> %b) {
;
; CHECK-GI-LABEL: uaddl_v8i16_v8i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
-; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
-; CHECK-GI-NEXT: ushll2 v4.4s, v0.8h, #0
-; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0
-; CHECK-GI-NEXT: uaddl v0.2d, v2.2s, v3.2s
-; CHECK-GI-NEXT: uaddl2 v1.2d, v2.4s, v3.4s
-; CHECK-GI-NEXT: uaddl v2.2d, v4.2s, v5.2s
-; CHECK-GI-NEXT: uaddl2 v3.2d, v4.4s, v5.4s
+; CHECK-GI-NEXT: uaddl v2.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: uaddl2 v3.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT: ushll v0.2d, v2.2s, #0
+; CHECK-GI-NEXT: ushll2 v1.2d, v2.4s, #0
+; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0
+; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0
; CHECK-GI-NEXT: ret
%c = zext <8 x i16> %a to <8 x i64>
%d = zext <8 x i16> %b to <8 x i64>
@@ -1484,14 +1460,12 @@ define <16 x i32> @uaddl_v16i8_v16i32(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: uaddl_v16i8_v16i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
-; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
-; CHECK-GI-NEXT: ushll2 v4.8h, v0.16b, #0
-; CHECK-GI-NEXT: ushll2 v5.8h, v1.16b, #0
-; CHECK-GI-NEXT: uaddl v0.4s, v2.4h, v3.4h
-; CHECK-GI-NEXT: uaddl2 v1.4s, v2.8h, v3.8h
-; CHECK-GI-NEXT: uaddl v2.4s, v4.4h, v5.4h
-; CHECK-GI-NEXT: uaddl2 v3.4s, v4.8h, v5.8h
+; CHECK-GI-NEXT: uaddl v2.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: uaddl2 v3.8h, v0.16b, v1.16b
+; CHECK-GI-NEXT: ushll v0.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll2 v1.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #0
+; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #0
; CHECK-GI-NEXT: ret
%c = zext <16 x i8> %a to <16 x i32>
%d = zext <16 x i8> %b to <16 x i32>
@@ -1520,26 +1494,20 @@ define <16 x i64> @uaddl_v16i8_v16i64(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: uaddl_v16i8_v16i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0
-; CHECK-GI-NEXT: ushll v3.8h, v1.8b, #0
-; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
-; CHECK-GI-NEXT: ushll2 v1.8h, v1.16b, #0
-; CHECK-GI-NEXT: ushll v4.4s, v2.4h, #0
-; CHECK-GI-NEXT: ushll2 v5.4s, v2.8h, #0
-; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #0
-; CHECK-GI-NEXT: ushll v6.4s, v0.4h, #0
-; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #0
-; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
-; CHECK-GI-NEXT: ushll2 v16.4s, v0.8h, #0
-; CHECK-GI-NEXT: ushll2 v17.4s, v1.8h, #0
-; CHECK-GI-NEXT: uaddl v0.2d, v4.2s, v2.2s
-; CHECK-GI-NEXT: uaddl2 v1.2d, v4.4s, v2.4s
-; CHECK-GI-NEXT: uaddl v2.2d, v5.2s, v3.2s
-; CHECK-GI-NEXT: uaddl2 v3.2d, v5.4s, v3.4s
-; CHECK-GI-NEXT: uaddl v4.2d, v6.2s, v7.2s
-; CHECK-GI-NEXT: uaddl2 v5.2d, v6.4s, v7.4s
-; CHECK-GI-NEXT: uaddl v6.2d, v16.2s, v17.2s
-; CHECK-GI-NEXT: uaddl2 v7.2d, v16.4s, v17.4s
+; CHECK-GI-NEXT: uaddl v2.8h, v0.8b, v1.8b
+; CHECK-GI-NEXT: uaddl2 v0.8h, v0.16b, v1.16b
+; CHECK-GI-NEXT: ushll v1.4s, v2.4h, #0
+; CHECK-GI-NEXT: ushll2 v3.4s, v2.8h, #0
+; CHECK-GI-NEXT: ushll v5.4s, v0.4h, #0
+; CHECK-GI-NEXT: ushll2 v7.4s, v0.8h, #0
+; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #0
+; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0
+; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0
+; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0
+; CHECK-GI-NEXT: ushll v4.2d, v5.2s, #0
+; CHECK-GI-NEXT: ushll2 v5.2d, v5.4s, #0
+; CHECK-GI-NEXT: ushll v6.2d, v7.2s, #0
+; CHECK-GI-NEXT: ushll2 v7.2d, v7.4s, #0
; CHECK-GI-NEXT: ret
%c = zext <16 x i8> %a to <16 x i64>
%d = zext <16 x i8> %b to <16 x i64>
@@ -1566,22 +1534,18 @@ define <16 x i64> @uaddl_v16i16_v16i64(<16 x i16> %a, <16 x i16> %b) {
;
; CHECK-GI-LABEL: uaddl_v16i16_v16i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v4.4s, v0.4h, #0
-; CHECK-GI-NEXT: ushll2 v5.4s, v0.8h, #0
-; CHECK-GI-NEXT: ushll v6.4s, v2.4h, #0
-; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0
-; CHECK-GI-NEXT: ushll2 v16.4s, v2.8h, #0
-; CHECK-GI-NEXT: ushll v17.4s, v3.4h, #0
-; CHECK-GI-NEXT: ushll2 v18.4s, v1.8h, #0
-; CHECK-GI-NEXT: ushll2 v19.4s, v3.8h, #0
-; CHECK-GI-NEXT: uaddl v0.2d, v4.2s, v6.2s
-; CHECK-GI-NEXT: uaddl2 v1.2d, v4.4s, v6.4s
-; CHECK-GI-NEXT: uaddl v2.2d, v5.2s, v16.2s
-; CHECK-GI-NEXT: uaddl2 v3.2d, v5.4s, v16.4s
-; CHECK-GI-NEXT: uaddl v4.2d, v7.2s, v17.2s
-; CHECK-GI-NEXT: uaddl2 v5.2d, v7.4s, v17.4s
-; CHECK-GI-NEXT: uaddl v6.2d, v18.2s, v19.2s
-; CHECK-GI-NEXT: uaddl2 v7.2d, v18.4s, v19.4s
+; CHECK-GI-NEXT: uaddl v4.4s, v0.4h, v2.4h
+; CHECK-GI-NEXT: uaddl2 v5.4s, v0.8h, v2.8h
+; CHECK-GI-NEXT: uaddl v6.4s, v1.4h, v3.4h
+; CHECK-GI-NEXT: uaddl2 v7.4s, v1.8h, v3.8h
+; CHECK-GI-NEXT: ushll v0.2d, v4.2s, #0
+; CHECK-GI-NEXT: ushll2 v1.2d, v4.4s, #0
+; CHECK-GI-NEXT: ushll v2.2d, v5.2s, #0
+; CHECK-GI-NEXT: ushll2 v3.2d, v5.4s, #0
+; CHECK-GI-NEXT: ushll v4.2d, v6.2s, #0
+; CHECK-GI-NEXT: ushll2 v5.2d, v6.4s, #0
+; CHECK-GI-NEXT: ushll v6.2d, v7.2s, #0
+; CHECK-GI-NEXT: ushll2 v7.2d, v7.4s, #0
; CHECK-GI-NEXT: ret
%c = zext <16 x i16> %a to <16 x i64>
%d = zext <16 x i16> %b to <16 x i64>
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add.ll b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
index ab7cea8dfb778..c9fe89aec8ad9 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-add.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
@@ -4725,94 +4725,102 @@ define i32 @full(ptr %p1, i32 noundef %s1, ptr %p2, i32 noundef %s2) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-GI-NEXT: // kill: def $w3 killed $w3 def $x3
-; CHECK-GI-NEXT: sxtw x8, w3
; CHECK-GI-NEXT: sxtw x9, w1
+; CHECK-GI-NEXT: sxtw x8, w3
; CHECK-GI-NEXT: ldr d0, [x0]
; CHECK-GI-NEXT: ldr d1, [x2]
; CHECK-GI-NEXT: add x10, x0, x9
; CHECK-GI-NEXT: add x11, x2, x8
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: ldr d2, [x10]
-; CHECK-GI-NEXT: add x10, x10, x9
-; CHECK-GI-NEXT: add x12, x11, x8
-; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-GI-NEXT: ldr d3, [x11]
-; CHECK-GI-NEXT: ldr d4, [x10]
-; CHECK-GI-NEXT: ldr d5, [x12]
-; CHECK-GI-NEXT: add x10, x10, x9
-; CHECK-GI-NEXT: add x11, x12, x8
-; CHECK-GI-NEXT: ushll v2.8h, v2.8b, #0
-; CHECK-GI-NEXT: ushll v3.8h, v3.8b, #0
-; CHECK-GI-NEXT: ushll v4.8h, v4.8b, #0
-; CHECK-GI-NEXT: ushll v5.8h, v5.8b, #0
-; CHECK-GI-NEXT: uabdl v6.4s, v0.4h, v1.4h
-; CHECK-GI-NEXT: uabdl2 v0.4s, v0.8h, v1.8h
+; CHECK-GI-NEXT: usubl v0.8h, v0.8b, v1.8b
; CHECK-GI-NEXT: ldr d1, [x10]
-; CHECK-GI-NEXT: ldr d7, [x11]
+; CHECK-GI-NEXT: ldr d2, [x11]
; CHECK-GI-NEXT: add x10, x10, x9
; CHECK-GI-NEXT: add x11, x11, x8
-; CHECK-GI-NEXT: uabdl v16.4s, v2.4h, v3.4h
-; CHECK-GI-NEXT: uabdl2 v2.4s, v2.8h, v3.8h
-; CHECK-GI-NEXT: uabdl v3.4s, v4.4h, v5.4h
-; CHECK-GI-NEXT: uabdl2 v4.4s, v4.8h, v5.8h
-; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-GI-NEXT: ushll v7.8h, v7.8b, #0
-; CHECK-GI-NEXT: ldr d5, [x10]
-; CHECK-GI-NEXT: ldr d17, [x11]
+; CHECK-GI-NEXT: usubl v1.8h, v1.8b, v2.8b
+; CHECK-GI-NEXT: ldr d3, [x10]
+; CHECK-GI-NEXT: ldr d4, [x11]
+; CHECK-GI-NEXT: sshll v5.4s, v0.4h, #0
+; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
+; CHECK-GI-NEXT: add x10, x10, x9
+; CHECK-GI-NEXT: add x11, x11, x8
+; CHECK-GI-NEXT: ldr d2, [x10]
; CHECK-GI-NEXT: add x10, x10, x9
+; CHECK-GI-NEXT: sshll v7.4s, v1.4h, #0
+; CHECK-GI-NEXT: sshll2 v1.4s, v1.8h, #0
+; CHECK-GI-NEXT: ldr d6, [x11]
; CHECK-GI-NEXT: add x11, x11, x8
-; CHECK-GI-NEXT: add v0.4s, v6.4s, v0.4s
-; CHECK-GI-NEXT: ushll v5.8h, v5.8b, #0
-; CHECK-GI-NEXT: ushll v17.8h, v17.8b, #0
-; CHECK-GI-NEXT: add v2.4s, v16.4s, v2.4s
-; CHECK-GI-NEXT: add v3.4s, v3.4s, v4.4s
-; CHECK-GI-NEXT: uabdl v4.4s, v1.4h, v7.4h
-; CHECK-GI-NEXT: uabdl2 v1.4s, v1.8h, v7.8h
-; CHECK-GI-NEXT: ldr d7, [x10]
+; CHECK-GI-NEXT: usubl v3.8h, v3.8b, v4.8b
+; CHECK-GI-NEXT: abs v5.4s, v5.4s
+; CHECK-GI-NEXT: abs v0.4s, v0.4s
+; CHECK-GI-NEXT: ldr d4, [x10]
; CHECK-GI-NEXT: ldr d16, [x11]
+; CHECK-GI-NEXT: abs v7.4s, v7.4s
+; CHECK-GI-NEXT: abs v1.4s, v1.4s
; CHECK-GI-NEXT: add x10, x10, x9
; CHECK-GI-NEXT: add x11, x11, x8
-; CHECK-GI-NEXT: ldr d18, [x10]
-; CHECK-GI-NEXT: ldr d20, [x10, x9]
-; CHECK-GI-NEXT: ldr d19, [x11]
-; CHECK-GI-NEXT: ldr d21, [x11, x8]
-; CHECK-GI-NEXT: uabdl v6.4s, v5.4h, v17.4h
-; CHECK-GI-NEXT: ushll v7.8h, v7.8b, #0
-; CHECK-GI-NEXT: ushll v16.8h, v16.8b, #0
-; CHECK-GI-NEXT: uabdl2 v5.4s, v5.8h, v17.8h
-; CHECK-GI-NEXT: ushll v17.8h, v18.8b, #0
-; CHECK-GI-NEXT: ushll v18.8h, v19.8b, #0
-; CHECK-GI-NEXT: add v1.4s, v4.4s, v1.4s
-; CHECK-GI-NEXT: ushll v4.8h, v20.8b, #0
-; CHECK-GI-NEXT: ushll v19.8h, v21.8b, #0
-; CHECK-GI-NEXT: addv s2, v2.4s
+; CHECK-GI-NEXT: usubl v2.8h, v2.8b, v6.8b
+; CHECK-GI-NEXT: ldr d6, [x10]
+; CHECK-GI-NEXT: ldr d17, [x11]
+; CHECK-GI-NEXT: add x10, x10, x9
+; CHECK-GI-NEXT: add x11, x11, x8
+; CHECK-GI-NEXT: usubl v4.8h, v4.8b, v16.8b
+; CHECK-GI-NEXT: sshll v16.4s, v3.4h, #0
+; CHECK-GI-NEXT: sshll2 v3.4s, v3.8h, #0
+; CHECK-GI-NEXT: add v0.4s, v5.4s, v0.4s
+; CHECK-GI-NEXT: add v1.4s, v7.4s, v1.4s
+; CHECK-GI-NEXT: ldr d5, [x10]
+; CHECK-GI-NEXT: ldr d7, [x11]
+; CHECK-GI-NEXT: sshll v18.4s, v2.4h, #0
+; CHECK-GI-NEXT: sshll2 v2.4s, v2.8h, #0
+; CHECK-GI-NEXT: usubl v6.8h, v6.8b, v17.8b
+; CHECK-GI-NEXT: ldr d17, [x11, x8]
+; CHECK-GI-NEXT: sshll v19.4s, v4.4h, #0
+; CHECK-GI-NEXT: usubl v5.8h, v5.8b, v7.8b
+; CHECK-GI-NEXT: ldr d7, [x10, x9]
+; CHECK-GI-NEXT: sshll2 v4.4s, v4.8h, #0
+; CHECK-GI-NEXT: abs v16.4s, v16.4s
+; CHECK-GI-NEXT: abs v3.4s, v3.4s
+; CHECK-GI-NEXT: abs v18.4s, v18.4s
+; CHECK-GI-NEXT: abs v2.4s, v2.4s
+; CHECK-GI-NEXT: usubl v7.8h, v7.8b, v17.8b
+; CHECK-GI-NEXT: sshll v17.4s, v6.4h, #0
+; CHECK-GI-NEXT: sshll2 v6.4s, v6.8h, #0
+; CHECK-GI-NEXT: abs v19.4s, v19.4s
+; CHECK-GI-NEXT: abs v4.4s, v4.4s
+; CHECK-GI-NEXT: add v3.4s, v16.4s, v3.4s
+; CHECK-GI-NEXT: sshll v16.4s, v5.4h, #0
+; CHECK-GI-NEXT: sshll2 v5.4s, v5.8h, #0
+; CHECK-GI-NEXT: add v2.4s, v18.4s, v2.4s
+; CHECK-GI-NEXT: abs v17.4s, v17.4s
+; CHECK-GI-NEXT: addv s1, v1.4s
+; CHECK-GI-NEXT: abs v6.4s, v6.4s
; CHECK-GI-NEXT: addv s0, v0.4s
+; CHECK-GI-NEXT: add v4.4s, v19.4s, v4.4s
; CHECK-GI-NEXT: addv s3, v3.4s
-; CHECK-GI-NEXT: uabdl v20.4s, v7.4h, v16.4h
-; CHECK-GI-NEXT: uabdl2 v7.4s, v7.8h, v16.8h
-; CHECK-GI-NEXT: add v5.4s, v6.4s, v5.4s
-; CHECK-GI-NEXT: uabdl v6.4s, v17.4h, v18.4h
-; CHECK-GI-NEXT: uabdl2 v16.4s, v17.8h, v18.8h
-; CHECK-GI-NEXT: uabdl v17.4s, v4.4h, v19.4h
-; CHECK-GI-NEXT: uabdl2 v4.4s, v4.8h, v19.8h
-; CHECK-GI-NEXT: fmov w8, s2
-; CHECK-GI-NEXT: addv s1, v1.4s
+; CHECK-GI-NEXT: sshll v18.4s, v7.4h, #0
+; CHECK-GI-NEXT: sshll2 v7.4s, v7.8h, #0
+; CHECK-GI-NEXT: abs v16.4s, v16.4s
+; CHECK-GI-NEXT: abs v5.4s, v5.4s
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: add v6.4s, v17.4s, v6.4s
+; CHECK-GI-NEXT: addv s2, v2.4s
; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: addv s4, v4.4s
; CHECK-GI-NEXT: fmov w10, s3
-; CHECK-GI-NEXT: add v7.4s, v20.4s, v7.4s
-; CHECK-GI-NEXT: add v0.4s, v17.4s, v4.4s
-; CHECK-GI-NEXT: addv s4, v5.4s
-; CHECK-GI-NEXT: add v2.4s, v6.4s, v16.4s
+; CHECK-GI-NEXT: abs v18.4s, v18.4s
+; CHECK-GI-NEXT: abs v7.4s, v7.4s
+; CHECK-GI-NEXT: add v1.4s, v16.4s, v5.4s
; CHECK-GI-NEXT: add w8, w8, w9
-; CHECK-GI-NEXT: fmov w9, s1
+; CHECK-GI-NEXT: addv s3, v6.4s
+; CHECK-GI-NEXT: fmov w9, s2
; CHECK-GI-NEXT: add w8, w10, w8
-; CHECK-GI-NEXT: addv s3, v7.4s
-; CHECK-GI-NEXT: addv s1, v2.4s
-; CHECK-GI-NEXT: addv s0, v0.4s
-; CHECK-GI-NEXT: add w8, w9, w8
-; CHECK-GI-NEXT: fmov w9, s4
+; CHECK-GI-NEXT: fmov w10, s4
+; CHECK-GI-NEXT: add v0.4s, v18.4s, v7.4s
+; CHECK-GI-NEXT: addv s1, v1.4s
; CHECK-GI-NEXT: add w8, w9, w8
; CHECK-GI-NEXT: fmov w9, s3
+; CHECK-GI-NEXT: add w8, w10, w8
+; CHECK-GI-NEXT: addv s0, v0.4s
; CHECK-GI-NEXT: add w8, w9, w8
; CHECK-GI-NEXT: fmov w9, s1
; CHECK-GI-NEXT: add w8, w9, w8
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