[llvm] [AArch64][GlobalISel] Push ADD/SUB through Extend Instructions (PR #90964)

[Matt Arsenault via llvm-commits]

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@@ -554,6 +554,55 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
   MI.eraseFromParent();
 }
 
+// Pushes ADD/SUB through extend instructions to decrease the number of extend
+// instruction at the end by allowing selection of {s|u}addl sooner
+
+// i32 add(i32 ext i8, i32 ext i8) => i32 ext(i16 add(i16 ext i8, i16 ext i8))
+bool matchPushAddSubExt(MachineInstr &MI, MachineRegisterInfo &MRI,
+                        Register DstReg, Register SrcReg1, Register SrcReg2) {
+  assert(MI.getOpcode() == TargetOpcode::G_ADD ||
+         MI.getOpcode() == TargetOpcode::G_SUB &&
+             "Expected a G_ADD or G_SUB instruction\n");
+
+  // Deal with vector types only
+  LLT DstTy = MRI.getType(DstReg);
+  if (!DstTy.isVector())
+    return false;
+
+  // Return true if G_{S|Z}EXT instruction is more than 2* source
+  Register ExtDstReg = MI.getOperand(1).getReg();
+  LLT ExtDstTy = MRI.getType(ExtDstReg);
+  LLT Ext1SrcTy = MRI.getType(SrcReg1);
+  LLT Ext2SrcTy = MRI.getType(SrcReg2);
+  if (((Ext1SrcTy.getScalarSizeInBits() == 8 &&
+        ExtDstTy.getScalarSizeInBits() == 32) ||
+       ((Ext1SrcTy.getScalarSizeInBits() == 8 ||
+         Ext1SrcTy.getScalarSizeInBits() == 16) &&
+        ExtDstTy.getScalarSizeInBits() == 64)) &&
+      Ext1SrcTy == Ext2SrcTy)
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arsenm wrote:

Can you rephrase the type constraints more generally? Like with free zext or something? And move to generic combines? 

https://github.com/llvm/llvm-project/pull/90964