[llvm] [AArch64][GlobalISel] Push ADD/SUB through Extend Instructions (PR #90964)

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git-clang-format --diff 1ef081b05c562936fc025dde39b444066d9d470f b91b94e4840f9e1d7556fd39a094d441be8b2fcb -- llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index ab6e3a4985..90b64c416b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -558,8 +558,8 @@ void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
 // instruction at the end by allowing selection of {s|u}addl sooner
 
 // i32 add(i32 ext i8, i32 ext i8) => i32 ext(i16 add(i16 ext i8, i16 ext i8))
-bool matchPushAddSubExt(
-    MachineInstr &MI, MachineRegisterInfo &MRI, Register DstReg, Register SrcReg1, Register SrcReg2) {
+bool matchPushAddSubExt(MachineInstr &MI, MachineRegisterInfo &MRI,
+                        Register DstReg, Register SrcReg1, Register SrcReg2) {
   assert(MI.getOpcode() == TargetOpcode::G_ADD ||
          MI.getOpcode() == TargetOpcode::G_SUB &&
              "Expected a G_ADD or G_SUB instruction\n");
@@ -569,7 +569,6 @@ bool matchPushAddSubExt(
   if (!DstTy.isVector())
     return false;
 
-
   // Return true if G_{S|Z}EXT instruction is more than 2* source
   Register ExtDstReg = MI.getOperand(1).getReg();
   LLT ExtDstTy = MRI.getType(ExtDstReg);
@@ -586,12 +585,12 @@ bool matchPushAddSubExt(
   return false;
 }
 
-void applyPushAddSubExt(
-    MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool isSExt, Register DstReg, Register SrcReg1, Register SrcReg2) {
+void applyPushAddSubExt(MachineInstr &MI, MachineRegisterInfo &MRI,
+                        MachineIRBuilder &B, bool isSExt, Register DstReg,
+                        Register SrcReg1, Register SrcReg2) {
   LLT SrcTy = MRI.getType(SrcReg1);
   LLT MidTy = SrcTy.changeElementSize(SrcTy.getScalarSizeInBits() * 2);
-  unsigned Opc =
-      isSExt ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
+  unsigned Opc = isSExt ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
   Register Ext1Reg = B.buildInstr(Opc, {MidTy}, {SrcReg1}).getReg(0);
   Register Ext2Reg = B.buildInstr(Opc, {MidTy}, {SrcReg2}).getReg(0);
   Register AddReg =

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https://github.com/llvm/llvm-project/pull/90964