[llvm] [RISCV] Refactor extract_subvector lowering slightly. NFC (PR #65391)

[Luke Lau via llvm-commits]

================
@@ -8664,17 +8665,15 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
   if (RemIdx == 0)
     return Op;
 
-  // Else we must shift our vector register directly to extract the subvector.
-  // Do this using VSLIDEDOWN.
+  // Else SubVecVT is a fractional LMUL and needs to be slid down.
+  assert(RISCVVType::decodeVLMUL(getLMUL(SubVecVT)).second);
----------------
lukel97 wrote:

The index=0 case doesn't necessarily guarantee that sizeof(SubVecVT) < sizeof(VecVT), consider an extract of v2i8 from an nxv2i8 at index 2. It's a well formed extract_subvector, but at vscale=1, sizeof(v2i8) == sizeof(nxv2i8)

I also tried the NoRegister assert, but as it turns out if both SubVecVT and VecVT are LMUL=1 or less, e.g v2i8 and nxv2i8, they'll both have the LMUL=1 register class and `decomposeSubvectorInsertExtractToSubRegs` will return NoRegister.

But if we get NoRegister then we don't end up performing the subregister extract anyway, because we only do it when `VecVT.bitsGT(getLMUL1VT(VecVT))`. I think we can put the assert in that branch.

https://github.com/llvm/llvm-project/pull/65391