[llvm] [RISCV] Refactor extract_subvector lowering slightly. NFC (PR #65391)

[Philip Reames via llvm-commits]

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@@ -8664,17 +8665,15 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
   if (RemIdx == 0)
     return Op;
 
-  // Else we must shift our vector register directly to extract the subvector.
-  // Do this using VSLIDEDOWN.
+  // Else SubVecVT is a fractional LMUL and needs to be slid down.
+  assert(RISCVVType::decodeVLMUL(getLMUL(SubVecVT)).second);
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preames wrote:

Inside decomposeSubvectorInsertExtractToSubRegs, there's a comment which reads:
  // Note that this is not guaranteed to find a subregister index, such as
  // when we are extracting from one VR type to another.

This seems to contradict your new assert here.

After thinking about it, I think that comment is stale because moving the index=0 case early adds a precondition to that routine that SubVecVT != VecVT, and thus sizeof(SubVecVT) < sizeof(VecVT).

If you agree, would you mind updating the comment to reflect that?  We've only changed the invariant for one of two callers, so we can't actually add the assert in the callee, but maybe right before the call for this caller?  And maybe add an assert that the result is not NoRegister?

https://github.com/llvm/llvm-project/pull/65391