[llvm] [RISCV] Refactor extract_subvector lowering slightly. NFC (PR #65391)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 6 05:00:18 PDT 2023
================
@@ -8664,17 +8665,15 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
if (RemIdx == 0)
return Op;
- // Else we must shift our vector register directly to extract the subvector.
- // Do this using VSLIDEDOWN.
+ // Else SubVecVT is a fractional LMUL and needs to be slid down.
+ assert(RISCVVType::decodeVLMUL(getLMUL(SubVecVT)).second);
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lukel97 wrote:
The only case I can think of decomposing would fail and we try to extract a subregister is when SubVecVT and VecVT have the same LMUL and the LMUL>1.
In that case though, the only valid index is 0:
> IDX must be a constant multiple of T's known minimum vector length. If T is a scalable vector, DX is first scaled by the runtime scaling factor of T. Elements IDX through (IDX + num_elements(T) - 1) must be valid VECTOR indices.
So we should have returned early by the precondition.
https://github.com/llvm/llvm-project/pull/65391
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