[llvm] [RISCV] Extract subregister if VLEN is known when lowering extract_subvector (PR #65392)

[Philip Reames via llvm-commits]

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@@ -8628,12 +8628,14 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
   if (OrigIdx == 0)
     return Op;
 
+  auto KnownVLen = Subtarget.getRealKnownVLen();
+
   // If the subvector vector is a fixed-length type, we cannot use subregister
-  // manipulation to simplify the codegen; we don't know which register of a
-  // LMUL group contains the specific subvector as we only know the minimum
-  // register size. Therefore we must slide the vector group down the full
-  // amount.
-  if (SubVecVT.isFixedLengthVector()) {
+  // manipulation to simplify the codegen if we don't know VLEN; we don't know
+  // which register of a LMUL group contains the specific subvector as we only
+  // know the minimum register size. Therefore we must slide the vector group
+  // down the full amount.
+  if (SubVecVT.isFixedLengthVector() && !KnownVLen) {
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preames wrote:

This isn't fully general.

Consider: 8 x i64 on V (a lmul4 type), extract the second <2 x i64> quarter.  We can still do know this is the first LMUL2 sub-register.  This doesn't allow us to slide less, but it does allow us to reduce the lmul for the slide.  

https://github.com/llvm/llvm-project/pull/65392