[PATCH] D154739: [RISCV] Check for alignment when selecting whole register loads/stores

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

So what we're saying is the -mattr=+unaligned-vector-mem that we made up does not apply to whole register load/store? but applies regular loads and store?



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Comment at: llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll:239
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vs2r.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
----------------
Doesn't vs2r.v have an EEW of 8?


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https://reviews.llvm.org/D154739