[PATCH] D154739: [RISCV] Check for alignment when selecting whole register loads/stores

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll:68
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl1re64.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; UNALIGNED-NEXT:    vle64.v v8, (a0)
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Couldn't we use vl1r.v?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154739/new/

https://reviews.llvm.org/D154739