[PATCH] D154739: [RISCV] Check for alignment when selecting whole register loads/stores

[Luke Lau via Phabricator via llvm-commits]

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As per the specification, whole register vector loads and stores may raise a
misaligned address exception "if the base address is not naturally aligned to
the larger of the size of the encoded EEW in bytes (EEW/8) or the
implementation’s smallest supported SEW size in bytes (SEWMIN/8)."

This patch adds a predicate to ensure the alignment is greater than or equal to
the EEW in bytes. It doesn't check SEWMIN however since the smallest SEW can be
with the standard extensions is 8 bytes.

Note that this doesn't fix the issue raised here:
https://reviews.llvm.org/D154536#inline-1495073


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154739

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

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