[PATCH] D154136: [RISCV] Add SEW to RISCVInversePseudoTable

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:512
+/// and is an implementation defined mapping.
+class SEWTo3BitSEW<int sew> {
+  bits<3> s = !cond(
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craig.topper wrote:
> Why do we need to compress it 3 bits in tablegen, but we use 8 bits in RISCVCustomBehaviour.cpp?
I can revert it to 8. I made it 3 because it looked like we were trying to pack tightly in this class. 3 bits ID as tight as you can get to represent this encoding. We can hold off on making it 3 until we’d like to add a field to the inverse table and we need the space. Let me know what you think. 


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  https://reviews.llvm.org/D154136/new/

https://reviews.llvm.org/D154136