[PATCH] D154136: [RISCV] Add SEW to RISCVInversePseudoTable

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:512
+/// and is an implementation defined mapping.
+class SEWTo3BitSEW<int sew> {
+  bits<3> s = !cond(
----------------
Why do we need to compress it 3 bits in tablegen, but we use 8 bits in RISCVCustomBehaviour.cpp?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154136/new/

https://reviews.llvm.org/D154136