[PATCH] D152937: [RISCV] Document overview of vector psuedos [nfc]
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 15 02:43:51 PDT 2023
luke added inline comments.
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.h:300
+ those lanes.
+ * "Undefined" - The bit pattern of the inactive lanes is unspecified, and
+ can be changed without impacting the semantics of the program. Note that
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Is undefined actually a policy, or just a common representation within the backend? Because I don’t think we can mix both tail undefined and mask undisturbed policies, or that there’s no way to represent it at least
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.h:323
+ from this representation.
+ * _TU - Can represent all three policy states. If passthrough is
+ IMPLICIT_DEF, then represents "undefined". Otherwise, policy operand
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Not for this patch, but should we standardise the terminology of passthrough vs. merge throughout the backend and pick one? My weak preference would be for passthrough as it’s less confusing with vmerge etc.
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https://reviews.llvm.org/D152937/new/
https://reviews.llvm.org/D152937
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