[PATCH] D152937: [RISCV] Document overview of vector psuedos [nfc]

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.h:299
+  the exact bit pattern of inactive lanes, or produce the bit pattern -1 for
+  those lanes.
+  * "Undefined" - The bit pattern of the inactive lanes is unspecified, and
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Adding upon this, the behavior of "bit pattern -1"" or "preserve" can be different among different lanes.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.h:321
+  the "undefined" state.  Note that terminology in code frequently refers to
+  these as "TA" which is confusing.  We're in the process of migrating away
+  from this representation.
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TA is abbreviation for tail agnostic.

I agree that the meaning is ambiguous, as

1. Unmasked intrinsics that model policy behavior, and set to tail-agnostic
2. Intrinsics that does not model a policy behavior

both share this same state.


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https://reviews.llvm.org/D152937