[PATCH] D152680: [RISCV][NFC] Improve encoding/decoding tests for Zbb instructions

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM, modulo one minor tweak to the rori on RV64 test.



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Comment at: llvm/test/MC/RISCV/rv64zbb-valid.s:13
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
+rori t0, t1, 31
+# CHECK-ASM-AND-OBJ: rori t0, t1, 0
----------------
It would make sense to test the wider shift amount supported on RV64 here


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D152680