[PATCH] D152680: [RISCV][NFC] Improve encoding/decoding tests for Zbb instructions

[Venkata Ramanaiah Nalamothu via Phabricator via llvm-commits]

RamNalamothu updated this revision to Diff 530845.
RamNalamothu added a comment.

Test the wider 6-bit shift amount for rori on RV64.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152680/new/

https://reviews.llvm.org/D152680

Files:
  llvm/test/MC/RISCV/rv32zbb-only-valid.s
  llvm/test/MC/RISCV/rv32zbb-valid.s
  llvm/test/MC/RISCV/rv64zbb-valid.s

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