[PATCH] D152726: [RISCV][GlobalISel] Legalize all ALU instructions, excluding w-instructions
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 12 10:57:59 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:40
+
+ if (ST.hasStdExtM()) {
+ getActionDefinitionsBuilder({G_MUL, G_SDIV, G_SREM, G_UDIV, G_UREM})
----------------
I don't see any command lines with -mattr=+m, so this branch isn't tested?
In fact there are no test cases for mul, udiv, urem, sdiv, or srem.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152726/new/
https://reviews.llvm.org/D152726
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