[PATCH] D152726: [RISCV][GlobalISel] Legalize all ALU instructions, excluding w-instructions

[Thorsten via Phabricator via llvm-commits]

tschuett added a comment.

As long as you are not interested in vectors, I used this pattern:

  getActionDefinitionsBuilder(G_FREEZE)
      .legalFor({s8, s16, s32, s64, p0})
      .widenScalarToNextPow2(0, /*Min=*/8)
      .clampScalar(0, s8, sMaxScalar);

clamp to legal range and widen to next power of two to handle weird cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152726/new/

https://reviews.llvm.org/D152726