[PATCH] D152726: [RISCV][GlobalISel] Legalize all ALU instructions, excluding w-instructions

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj planned changes to this revision.
nitinjohnraj added a comment.

Add tests for smaller sizes, mul/div/rem variants.



================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:40
+
+  if (ST.hasStdExtM()) {
+    getActionDefinitionsBuilder({G_MUL, G_SDIV, G_SREM, G_UDIV, G_UREM})
----------------
craig.topper wrote:
> I don't see any command lines with -mattr=+m, so this branch isn't tested?
> 
> In fact there are no test cases for mul, udiv, urem, sdiv, or srem.
You're right, I'll add these.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152726/new/

https://reviews.llvm.org/D152726