[PATCH] D150969: [AArch64] Try to convert two XTN and two SMLSL to UZP1, SMLSL and SMLSL2

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Sounds good. Is the idea to expand this to check the uses of the original EXTRACT_SUBVECTOR's operands to see if there is another long mul that can use the other operand of the uzip?



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22417
+    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+    SDValue DUP = TLI.LowerOperation(TRUNCOP, DAG);
+    if (DUP.getOpcode() == AArch64ISD::DUP)
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Can this use maybe isSplatValue, to avoid the call to LowerOperation.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22426
+  // Create uzp1 and extract_high.
+  SDValue HighIdx = (TRUNC == RHS) ? LHS.getOperand(1) : RHS.getOperand(1);
+  EVT TRUNCVT = TRUNC.getValueType();
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It looks like LHS/RHS could be a bitcast from isEssentiallyExtractHighSubvector.


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  https://reviews.llvm.org/D150969/new/

https://reviews.llvm.org/D150969