[PATCH] D150969: [AArch64] Try to convert two XTN and two SMLSL to UZP1, SMLSL and SMLSL2

JinGu Kang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 31 04:00:51 PDT 2023


jaykang10 added a comment.

In D150969#4383791 <https://reviews.llvm.org/D150969#4383791>, @dmgreen wrote:

> Sounds good. Is the idea to expand this to check the uses of the original EXTRACT_SUBVECTOR's operands to see if there is another long mul that can use the other operand of the uzip?

Yep, as @efriedma suggested, first, we handle the mul high with uzp1 and then we will try to handle other instructions based on the uzp1.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22417
+    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+    SDValue DUP = TLI.LowerOperation(TRUNCOP, DAG);
+    if (DUP.getOpcode() == AArch64ISD::DUP)
----------------
dmgreen wrote:
> Can this use maybe isSplatValue, to avoid the call to LowerOperation.
Yep, you are right.
Let me update it.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22426
+  // Create uzp1 and extract_high.
+  SDValue HighIdx = (TRUNC == RHS) ? LHS.getOperand(1) : RHS.getOperand(1);
+  EVT TRUNCVT = TRUNC.getValueType();
----------------
dmgreen wrote:
> It looks like LHS/RHS could be a bitcast from isEssentiallyExtractHighSubvector.
Yep, you are right.
Let me update it.


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https://reviews.llvm.org/D150969



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