[PATCH] D151561: [RISCV][InsertVSETVLI] Avoid vmv.s.x SEW toggle if at start of block

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-transpose.ll:124
 ; CHECK-NEXT:    li a0, 10
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
 ; CHECK-NEXT:    vmv.s.x v0, a0
----------------
After rebasing a lot of tests have changed. I'm not sure why the mask undefined isn't being propagated back up to the first vsetivli – will investigate


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151561/new/

https://reviews.llvm.org/D151561