[PATCH] D151561: [RISCV][InsertVSETVLI] Avoid vmv.s.x SEW toggle if at start of block

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 526114.
luke added a comment.

Rebase and update tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151561/new/

https://reviews.llvm.org/D151561

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-transpose.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

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