[PATCH] D76354: [RISCV][GlobalISel] Legalize types for ALU operations
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 22 13:50:07 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:147
+ case TargetOpcode::G_SHL:
+ case TargetOpcode::G_ASHR:
+ case TargetOpcode::G_LSHR:
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Why is ASHR legalized with a ZExtInReg?
================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h:21
class RISCVSubtarget;
+class MachineIRBuilder;
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https://reviews.llvm.org/D76354/new/
https://reviews.llvm.org/D76354
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