[PATCH] D76354: [RISCV][GlobalISel] Legalize types for ALU operations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:106
+
+  auto NewOp0 = MIRBuilder.buildAnyExt(s64, MI.getOperand(1).getReg());
+  auto NewOp1 = MIRBuilder.buildAnyExt(s64, MI.getOperand(2).getReg());
----------------
Using AnyExt for operands of promoted SDIV/SREM is incorrect from the semantics of the Generic MachineIR. That puts garbage in the upper elements. 

@arsenm do you agree?


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Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:122
+
+  auto NewOp0 = MIRBuilder.buildAnyExt(s64, MI.getOperand(1).getReg());
+  auto NewOp1 = MIRBuilder.buildAnyExt(s64, MI.getOperand(2).getReg());
----------------
This also seems wrong for the semantics of the generic IR.

G_SHL needs operand 1 zero extend. Operand 0 can be zero extend.
G_ASHR needs operand 0 sign extended and operand 0 zero extended
G_LSHR, G_UDIV and G_UREM needs both operands zero extended.

@arsenm do you agree?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76354/new/

https://reviews.llvm.org/D76354