[PATCH] D144229: [RISCV] Select signed and unsigned bitfield extracts for XTHeadBb

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1022
           if (C2 + 32 == Leading) {
             SDNode *SRLIW = CurDAG->getMachineNode(
                 RISCV::SRLIW, DL, VT, X, CurDAG->getTargetConstant(C2, DL, VT));
----------------
Just to confirm, do you want th.extu preferred over this single SRLIW code?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144229/new/

https://reviews.llvm.org/D144229