[PATCH] D144229: [RISCV] Select signed and unsigned bitfield extracts for XTHeadBb
Philipp Tomsich via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 17 11:30:43 PST 2023
philipp.tomsich marked an inline comment as done.
philipp.tomsich added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1022
if (C2 + 32 == Leading) {
SDNode *SRLIW = CurDAG->getMachineNode(
RISCV::SRLIW, DL, VT, X, CurDAG->getTargetConstant(C2, DL, VT));
----------------
craig.topper wrote:
> Just to confirm, do you want th.extu preferred over this single SRLIW code?
I was about to say "Yes.", but just changed my mind: the standard instruction should always be preferred, if no performance difference (giving the vendor an easier way to eventually deprecate a custom extension by expanding into multiple u-ops).
So I'll change this one more time.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144229/new/
https://reviews.llvm.org/D144229
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