[PATCH] D144229: [RISCV] Select signed and unsigned bitfield extracts for XTHeadBb
Philipp Tomsich via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 17 11:19:00 PST 2023
philipp.tomsich marked 2 inline comments as done.
philipp.tomsich added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:698
+ const unsigned Msb = MsbPlusOne - 1;
+ const unsigned Lsb = RightShAmt - LeftShAmt;
+
----------------
craig.topper wrote:
> What if LeftShAmt > RightShAmt?
Thanks! I added a test-case as well.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144229/new/
https://reviews.llvm.org/D144229
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