[PATCH] D144070: [llvm][GenericUniformity] Prevent assert while calculating temporal divergence

[Yashwant Singh via Phabricator via llvm-commits]

yassingh added inline comments.


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Comment at: llvm/lib/CodeGen/MachineUniformityAnalysis.cpp:108
+    // assert(Reg.isVirtual());
+    if (Reg.isPhysical())
+      continue;
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sameerds wrote:
> What does it mean to continue here? Is it true that a physical register cannot be written inside the cycle? A comment explaining why will be useful.
Didn't get around to putting a lot of thought into it. Physical register operands need to be handled separately, which might also include sub-cases if it's an exec mask or function parameters/return values, etc. Continue here is just a placeholder until we have a way to deal with them.  


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Comment at: llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/uses-value-from-cycle.mir:4
+--- |
+  define amdgpu_cs void @f2() #0 {
+  bb:
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arsenm wrote:
> Shouldn't need IR section?
I took the tests from [[ https://github.com/llvm/llvm-project/issues/60638 | #60638]] (extracted the GMIR input that was fed to uniformity analysis).  I wasn't able to use @llvm.amdgcn.raw.atomic.buffer.load without including the IR section. Is there a workaround? 


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