[PATCH] D144070: [llvm][GenericUniformity] Prevent assert while calculating temporal divergence

[Sameer Sahasrabuddhe via Phabricator via llvm-commits]

sameerds added inline comments.


================
Comment at: llvm/lib/CodeGen/MachineUniformityAnalysis.cpp:108
+    // assert(Reg.isVirtual());
+    if (Reg.isPhysical())
+      continue;
----------------
yassingh wrote:
> sameerds wrote:
> > What does it mean to continue here? Is it true that a physical register cannot be written inside the cycle? A comment explaining why will be useful.
> Didn't get around to putting a lot of thought into it. Physical register operands need to be handled separately, which might also include sub-cases if it's an exec mask or function parameters/return values, etc. Continue here is just a placeholder until we have a way to deal with them.  
But if the exact conclusion is not known, then the correct conclusion is to be conservative. For example, it is always safer to assume that a value is divergent rather than assuming that it is uniform. In this particular case, it means that if we don't know whether the physical register was defined inside the cycle, then it is safer to assume that it was, and hence return true. Such a register will then be marked divergent by the caller.


Repository:
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  https://reviews.llvm.org/D144070/new/

https://reviews.llvm.org/D144070