[PATCH] D144070: [llvm][GenericUniformity] Prevent assert while calculating temporal divergence

[Sameer Sahasrabuddhe via Phabricator via llvm-commits]

sameerds added inline comments.


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Comment at: llvm/lib/CodeGen/MachineUniformityAnalysis.cpp:108
+    // assert(Reg.isVirtual());
+    if (Reg.isPhysical())
+      continue;
----------------
What does it mean to continue here? Is it true that a physical register cannot be written inside the cycle? A comment explaining why will be useful.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144070/new/

https://reviews.llvm.org/D144070