[llvm] 0b432df - [X86] Add DAG tests showing the failure to reassociate IMINMAX nodes to fold constant operands
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 21 07:28:58 PST 2023
Author: Simon Pilgrim
Date: 2023-01-21T15:24:49Z
New Revision: 0b432dfaf74ab80d60cb04fa0332650cb53ff453
URL: https://github.com/llvm/llvm-project/commit/0b432dfaf74ab80d60cb04fa0332650cb53ff453
DIFF: https://github.com/llvm/llvm-project/commit/0b432dfaf74ab80d60cb04fa0332650cb53ff453.diff
LOG: [X86] Add DAG tests showing the failure to reassociate IMINMAX nodes to fold constant operands
Test coverage for Issue #58110
Added:
Modified:
llvm/test/CodeGen/X86/combine-smax.ll
llvm/test/CodeGen/X86/combine-smin.ll
llvm/test/CodeGen/X86/combine-umax.ll
llvm/test/CodeGen/X86/combine-umin.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/combine-smax.ll b/llvm/test/CodeGen/X86/combine-smax.ll
index 32499af80dd6..efaeb97b89d6 100644
--- a/llvm/test/CodeGen/X86/combine-smax.ll
+++ b/llvm/test/CodeGen/X86/combine-smax.ll
@@ -45,3 +45,38 @@ define <16 x i8> @test_v16i8_nosignbit(<16 x i8> %a, <16 x i8> %b) {
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4
}
+
+define <16 x i8> @test_v16i8_reassociation(<16 x i8> %a) {
+; SSE2-LABEL: test_v16i8_reassociation:
+; SSE2: # %bb.0:
+; SSE2-NEXT: pxor %xmm1, %xmm1
+; SSE2-NEXT: movdqa %xmm0, %xmm2
+; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
+; SSE2-NEXT: pand %xmm2, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_v16i8_reassociation:
+; SSE41: # %bb.0:
+; SSE41-NEXT: pxor %xmm1, %xmm1
+; SSE41-NEXT: pmaxsb %xmm1, %xmm0
+; SSE41-NEXT: pmaxsb %xmm1, %xmm0
+; SSE41-NEXT: retq
+;
+; SSE42-LABEL: test_v16i8_reassociation:
+; SSE42: # %bb.0:
+; SSE42-NEXT: pxor %xmm1, %xmm1
+; SSE42-NEXT: pmaxsb %xmm1, %xmm0
+; SSE42-NEXT: pmaxsb %xmm1, %xmm0
+; SSE42-NEXT: retq
+;
+; AVX-LABEL: test_v16i8_reassociation:
+; AVX: # %bb.0:
+; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %1 = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %a, <16 x i8> zeroinitializer)
+ %2 = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %1, <16 x i8> zeroinitializer)
+ ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.smax.v16i8(<16 x i8> %x, <16 x i8> %y)
diff --git a/llvm/test/CodeGen/X86/combine-smin.ll b/llvm/test/CodeGen/X86/combine-smin.ll
index 2b398734c9d2..b228b153f6ee 100644
--- a/llvm/test/CodeGen/X86/combine-smin.ll
+++ b/llvm/test/CodeGen/X86/combine-smin.ll
@@ -45,3 +45,40 @@ define <16 x i8> @test_v16i8_nosignbit(<16 x i8> %a, <16 x i8> %b) {
%4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
ret <16 x i8> %4
}
+
+define <16 x i8> @test_v16i8_reassociation(<16 x i8> %a) {
+; SSE2-LABEL: test_v16i8_reassociation:
+; SSE2: # %bb.0:
+; SSE2-NEXT: pxor %xmm1, %xmm1
+; SSE2-NEXT: pxor %xmm2, %xmm2
+; SSE2-NEXT: pcmpgtb %xmm0, %xmm2
+; SSE2-NEXT: pand %xmm2, %xmm0
+; SSE2-NEXT: pcmpgtb %xmm0, %xmm1
+; SSE2-NEXT: pand %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_v16i8_reassociation:
+; SSE41: # %bb.0:
+; SSE41-NEXT: pxor %xmm1, %xmm1
+; SSE41-NEXT: pminsb %xmm1, %xmm0
+; SSE41-NEXT: pminsb %xmm1, %xmm0
+; SSE41-NEXT: retq
+;
+; SSE42-LABEL: test_v16i8_reassociation:
+; SSE42: # %bb.0:
+; SSE42-NEXT: pxor %xmm1, %xmm1
+; SSE42-NEXT: pminsb %xmm1, %xmm0
+; SSE42-NEXT: pminsb %xmm1, %xmm0
+; SSE42-NEXT: retq
+;
+; AVX-LABEL: test_v16i8_reassociation:
+; AVX: # %bb.0:
+; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %1 = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %a, <16 x i8> zeroinitializer)
+ %2 = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %1, <16 x i8> zeroinitializer)
+ ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.smin.v16i8(<16 x i8> %x, <16 x i8> %y)
diff --git a/llvm/test/CodeGen/X86/combine-umax.ll b/llvm/test/CodeGen/X86/combine-umax.ll
index 16a177cf0c98..fbfdb0b5b627 100644
--- a/llvm/test/CodeGen/X86/combine-umax.ll
+++ b/llvm/test/CodeGen/X86/combine-umax.ll
@@ -41,3 +41,37 @@ define <8 x i16> @test_v8i16_nosignbit(<8 x i16> %a, <8 x i16> %b) {
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4
}
+
+define <16 x i8> @test_v16i8_reassociation(<16 x i8> %a) {
+; SSE2-LABEL: test_v16i8_reassociation:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
+; SSE2-NEXT: pmaxub %xmm1, %xmm0
+; SSE2-NEXT: pmaxub %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_v16i8_reassociation:
+; SSE41: # %bb.0:
+; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
+; SSE41-NEXT: pmaxub %xmm1, %xmm0
+; SSE41-NEXT: pmaxub %xmm1, %xmm0
+; SSE41-NEXT: retq
+;
+; SSE42-LABEL: test_v16i8_reassociation:
+; SSE42: # %bb.0:
+; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
+; SSE42-NEXT: pmaxub %xmm1, %xmm0
+; SSE42-NEXT: pmaxub %xmm1, %xmm0
+; SSE42-NEXT: retq
+;
+; AVX-LABEL: test_v16i8_reassociation:
+; AVX: # %bb.0:
+; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
+; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %1 = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
+ %2 = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
+ ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.umax.v16i8(<16 x i8> %x, <16 x i8> %y)
diff --git a/llvm/test/CodeGen/X86/combine-umin.ll b/llvm/test/CodeGen/X86/combine-umin.ll
index 6399b6b148ac..0b1115a19948 100644
--- a/llvm/test/CodeGen/X86/combine-umin.ll
+++ b/llvm/test/CodeGen/X86/combine-umin.ll
@@ -58,3 +58,37 @@ define <8 x i16> @test_v8i16_nosignbit(<8 x i16> %a, <8 x i16> %b) {
%4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
ret <8 x i16> %4
}
+
+define <16 x i8> @test_v16i8_reassociation(<16 x i8> %a) {
+; SSE2-LABEL: test_v16i8_reassociation:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
+; SSE2-NEXT: pminub %xmm1, %xmm0
+; SSE2-NEXT: pminub %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: test_v16i8_reassociation:
+; SSE41: # %bb.0:
+; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
+; SSE41-NEXT: pminub %xmm1, %xmm0
+; SSE41-NEXT: pminub %xmm1, %xmm0
+; SSE41-NEXT: retq
+;
+; SSE42-LABEL: test_v16i8_reassociation:
+; SSE42: # %bb.0:
+; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
+; SSE42-NEXT: pminub %xmm1, %xmm0
+; SSE42-NEXT: pminub %xmm1, %xmm0
+; SSE42-NEXT: retq
+;
+; AVX-LABEL: test_v16i8_reassociation:
+; AVX: # %bb.0:
+; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
+; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %1 = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
+ %2 = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
+ ret <16 x i8> %2
+}
+declare <16 x i8> @llvm.umin.v16i8(<16 x i8> %x, <16 x i8> %y)
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