[PATCH] D142284: [DAG] Enable reassociate for SMAX/SMIN/UMAX/UMIN nodes

[Simon Pilgrim via Phabricator via llvm-commits]

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This helps us fold a number of cases where we're clamping chains of values with constant min/max values.

There is an instruction increase in the vtrunc_v128i32_v128i64 test as what had been chains of umin(umin(umin(x,c1),c2),c3), created by multiple levels of SplitEVL legalization calls, are flattened, resulting in better instruction parallelism but also an increase in in-flight values. This is a common issue with node reassociation, so I'm not sure if this is of any particular concern?

Fixes #58110


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142284

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
  llvm/test/CodeGen/X86/combine-smax.ll
  llvm/test/CodeGen/X86/combine-smin.ll
  llvm/test/CodeGen/X86/combine-umax.ll
  llvm/test/CodeGen/X86/combine-umin.ll

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