[PATCH] D137704: [RISCV] Make lowerVECTOR_SHUFFLEAsVNSRL support more vnsrl shuffle pattern.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2924
+      getContainerForFixedLengthVector(DAG, WidenVT, Subtarget);
+  // Do bitcast first, then convert it to scalable vector.
+  SDValue WidenSrc = DAG.getBitcast(WidenVT, Src);
----------------
Why did you change the order of bitcast and conversion?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137704/new/

https://reviews.llvm.org/D137704