[PATCH] D137704: [RISCV] Make lowerVECTOR_SHUFFLEAsVNSRL support more vnsrl shuffle pattern.

[Han-Kuan Chen via Phabricator via llvm-commits]

HanKuanChen added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2924
+      getContainerForFixedLengthVector(DAG, WidenVT, Subtarget);
+  // Do bitcast first, then convert it to scalable vector.
+  SDValue WidenSrc = DAG.getBitcast(WidenVT, Src);
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craig.topper wrote:
> Why did you change the order of bitcast and conversion?
> Why did you change the order of bitcast and conversion?

Example: `Src` is `v4i32`.
If we do bitcast then conversion, we get `v2i64` and `nxv1i64`.
If we do conversion then bitcast, we only get `nxv1i32` because `nxv1i32` and `nxv1i64` do not have same size.


Repository:
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  https://reviews.llvm.org/D137704/new/

https://reviews.llvm.org/D137704