[PATCH] D137069: [AArch64] Support all extend op for pattern: (ExtendNode - Y) + Z --> (Z - Y) + ExtendNode

chenglin.bi via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 8 01:46:11 PST 2022


bcl5980 added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16915
+    EVT SrcVT;
+    if (Opcode == ISD::SIGN_EXTEND_INREG)
+      SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
----------------
dmgreen wrote:
> Do you have tests for the other cases?
Not sure how to generate  ISD::ANY_EXTEND/ISD::SIGN_EXTEND_INREG from llvm-ir. Can you give me some suggestions for that?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16928
+  } else if (Opcode == ISD::SHL || Opcode == ISD::SRL || Opcode == ISD::SRA) {
+    // Do we need to consider overflow here?
+    return isa<ConstantSDNode>(N.getOperand(1));
----------------
dmgreen wrote:
> What overflow are you thinking of? Shifting past the bitwidth?
Yeah, I'm not sure if we can do this when the shift amount is larger than bitwidth.


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  https://reviews.llvm.org/D137069/new/

https://reviews.llvm.org/D137069



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