[PATCH] D137069: [AArch64] Support all extend op for pattern: (ExtendNode - Y) + Z --> (Z - Y) + ExtendNode

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16915
+    EVT SrcVT;
+    if (Opcode == ISD::SIGN_EXTEND_INREG)
+      SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
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bcl5980 wrote:
> dmgreen wrote:
> > Do you have tests for the other cases?
> Not sure how to generate  ISD::ANY_EXTEND/ISD::SIGN_EXTEND_INREG from llvm-ir. Can you give me some suggestions for that?
SIGN_EXTEND_INREG is usually `lsl 48; ashr 48`. Any extend can be difficult (especially if we expect the value to be used). Adding some extra 64bit tests would be useful too, for the different And cases for example.


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  https://reviews.llvm.org/D137069/new/

https://reviews.llvm.org/D137069