[PATCH] D137069: [AArch64] Support all extend op for pattern: (ExtendNode - Y) + Z --> (Z - Y) + ExtendNode

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16910
+/// Check an node can be extend or not
+static bool canbeExtend(SDValue N) {
+  unsigned Opcode = N.getOpcode();
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Perhaps change canbeExtend to isExtendOrShiftOperand, or something like it?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16915
+    EVT SrcVT;
+    if (Opcode == ISD::SIGN_EXTEND_INREG)
+      SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
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Do you have tests for the other cases?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16928
+  } else if (Opcode == ISD::SHL || Opcode == ISD::SRL || Opcode == ISD::SRA) {
+    // Do we need to consider overflow here?
+    return isa<ConstantSDNode>(N.getOperand(1));
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What overflow are you thinking of? Shifting past the bitwidth?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137069/new/

https://reviews.llvm.org/D137069