[llvm] 5800fb4 - [RISCV] Remove check and update test file in D121183

[via llvm-commits]

Author: luxufan
Date: 2022-03-24T00:48:52+08:00
New Revision: 5800fb41a6b95797e0dc9fe009bc7183ab370b17

URL: https://github.com/llvm/llvm-project/commit/5800fb41a6b95797e0dc9fe009bc7183ab370b17
DIFF: https://github.com/llvm/llvm-project/commit/5800fb41a6b95797e0dc9fe009bc7183ab370b17.diff

LOG: [RISCV] Remove check and update test file in D121183

Differential Revision: https://reviews.llvm.org/D122290

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
    llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
    llvm/test/MC/RISCV/mattr-invalid-combination.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 165ec7c5d19ae..917d93479f180 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -80,16 +80,7 @@ static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
   if (CPU.empty() || CPU == "generic")
     CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
 
-  MCSubtargetInfo *STI =
-      createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
-
-  // Check if Feature string is valid
-  auto ISAInfo =
-      RISCVFeatures::parseFeatureBits(TT.isArch64Bit(), STI->getFeatureBits());
-  if (!ISAInfo)
-    report_fatal_error(ISAInfo.takeError());
-  else
-    return STI;
+  return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
 }
 
 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,

diff  --git a/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll b/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
index f25950828333e..e5bdb96fd0741 100644
--- a/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
+++ b/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
@@ -2,4 +2,4 @@
 ; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \
 ; RUN:   | FileCheck -check-prefix=RV64E %s
 
-; RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32'
+; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target

diff  --git a/llvm/test/MC/RISCV/mattr-invalid-combination.s b/llvm/test/MC/RISCV/mattr-invalid-combination.s
index 16c72680aa586..f75fd3723ed49 100644
--- a/llvm/test/MC/RISCV/mattr-invalid-combination.s
+++ b/llvm/test/MC/RISCV/mattr-invalid-combination.s
@@ -1,4 +1,4 @@
 # RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \
 # RUN:   | FileCheck %s -check-prefix=RV64E
 
-# RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32'
+# RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target