[llvm] cac9773 - [SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-03-23T09:52:07-07:00
New Revision: cac9773dccd95cd442d2852b7ced0a8a311504f6

URL: https://github.com/llvm/llvm-project/commit/cac9773dccd95cd442d2852b7ced0a8a311504f6
DIFF: https://github.com/llvm/llvm-project/commit/cac9773dccd95cd442d2852b7ced0a8a311504f6.diff

LOG: [SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo

Instead of using operator[], use DenseMap::find to prevent default
constructing an entry if it isn't already in the map.

Also simplify a condition to check for 0 instead of a virtual register.
I'm pretty sure we can only get 0 or a virtual register out of the value
map.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index b49455111a468..e39ad73cf20c9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -445,9 +445,14 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
   unsigned BitWidth = IntVT.getSizeInBits();
 
-  Register DestReg = ValueMap[PN];
-  if (!Register::isVirtualRegister(DestReg))
+  auto It = ValueMap.find(PN);
+  if (It == ValueMap.end())
     return;
+
+  Register DestReg = It->second;
+  if (DestReg == 0)
+    return
+  assert(Register::isVirtualRegister(DestReg) && "Expected a virtual reg");
   LiveOutRegInfo.grow(DestReg);
   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];