[llvm] 227496d - [RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 23 09:50:11 PDT 2022
Author: luxufan
Date: 2022-03-24T00:48:52+08:00
New Revision: 227496dc09cf46df233aad041d6dc6113822e4bb
URL: https://github.com/llvm/llvm-project/commit/227496dc09cf46df233aad041d6dc6113822e4bb
DIFF: https://github.com/llvm/llvm-project/commit/227496dc09cf46df233aad041d6dc6113822e4bb.diff
LOG: [RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
In the past, when construct RISCVAsmBackend, MCTargetOptions.ABIName would be passed and stored in RISCVAsmBackend.
But MCTargetOptions.ABIName can only be specified by -target-abi xxx in command line, if the .ll file has target-abi attribute, the codegen module will ignore it. And the generated object file would have incorrect EFlags value.
https://github.com/llvm/llvm-project/issues/50591 also caused by this problem.
This patch override the AsmPrinter::emitFunctionEntryLabel function and use it to set the target abi value that get from .ll file's target-abi attribute. And storing the target-abi in RISCVTargetStreamer instead of RISCVAsmBackend.
Differential Revision: https://reviews.llvm.org/D121183
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/test/CodeGen/RISCV/module-target-abi2.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index f4bb8aba0ec1c..c34757750bf33 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -256,6 +256,11 @@ class RISCVAsmParser : public MCTargetAsmParser {
"target-abi)\n";
}
+ // Use computeTargetABI to check if ABIName is valid. If invalid, output
+ // error message.
+ RISCVABI::computeTargetABI(STI.getTargetTriple(), STI.getFeatureBits(),
+ ABIName);
+
const MCObjectFileInfo *MOFI = Parser.getContext().getObjectFileInfo();
ParserOptions.IsPicEnabled = MOFI->isPositionIndependent();
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
index 241edd369d4ea..5d62c3a8b0dfc 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
@@ -27,15 +27,12 @@ class RISCVAsmBackend : public MCAsmBackend {
bool Is64Bit;
bool ForceRelocs = false;
const MCTargetOptions &TargetOptions;
- RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
public:
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
const MCTargetOptions &Options)
: MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
TargetOptions(Options) {
- TargetABI = RISCVABI::computeTargetABI(
- STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName());
RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
}
~RISCVAsmBackend() override = default;
@@ -103,7 +100,6 @@ class RISCVAsmBackend : public MCAsmBackend {
const MCSubtargetInfo *STI) const override;
const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
- RISCVABI::ABI getTargetABI() const { return TargetABI; }
};
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 075a0d56ff9d2..88c417e974eb8 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -23,7 +23,6 @@
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCValue.h"
-#include "llvm/Support/Casting.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/RISCVAttributes.h"
@@ -32,38 +31,12 @@ using namespace llvm;
// This part is for ELF object output.
RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S,
const MCSubtargetInfo &STI)
- : RISCVTargetStreamer(S), CurrentVendor("riscv") {
+ : RISCVTargetStreamer(S), CurrentVendor("riscv"), STI(STI) {
MCAssembler &MCA = getStreamer().getAssembler();
const FeatureBitset &Features = STI.getFeatureBits();
auto &MAB = static_cast<RISCVAsmBackend &>(MCA.getBackend());
- RISCVABI::ABI ABI = MAB.getTargetABI();
- assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
-
- unsigned EFlags = MCA.getELFHeaderEFlags();
-
- if (Features[RISCV::FeatureStdExtC])
- EFlags |= ELF::EF_RISCV_RVC;
-
- switch (ABI) {
- case RISCVABI::ABI_ILP32:
- case RISCVABI::ABI_LP64:
- break;
- case RISCVABI::ABI_ILP32F:
- case RISCVABI::ABI_LP64F:
- EFlags |= ELF::EF_RISCV_FLOAT_ABI_SINGLE;
- break;
- case RISCVABI::ABI_ILP32D:
- case RISCVABI::ABI_LP64D:
- EFlags |= ELF::EF_RISCV_FLOAT_ABI_DOUBLE;
- break;
- case RISCVABI::ABI_ILP32E:
- EFlags |= ELF::EF_RISCV_RVE;
- break;
- case RISCVABI::ABI_Unknown:
- llvm_unreachable("Improperly initialised target ABI");
- }
-
- MCA.setELFHeaderEFlags(EFlags);
+ setTargetABI(RISCVABI::computeTargetABI(STI.getTargetTriple(), Features,
+ MAB.getTargetOptions().getABIName()));
}
MCELFStreamer &RISCVTargetELFStreamer::getStreamer() {
@@ -174,6 +147,39 @@ size_t RISCVTargetELFStreamer::calculateContentSize() const {
return Result;
}
+void RISCVTargetELFStreamer::finish() {
+ RISCVTargetStreamer::finish();
+ MCAssembler &MCA = getStreamer().getAssembler();
+ const FeatureBitset &Features = STI.getFeatureBits();
+ RISCVABI::ABI ABI = getTargetABI();
+
+ unsigned EFlags = MCA.getELFHeaderEFlags();
+
+ if (Features[RISCV::FeatureStdExtC])
+ EFlags |= ELF::EF_RISCV_RVC;
+
+ switch (ABI) {
+ case RISCVABI::ABI_ILP32:
+ case RISCVABI::ABI_LP64:
+ break;
+ case RISCVABI::ABI_ILP32F:
+ case RISCVABI::ABI_LP64F:
+ EFlags |= ELF::EF_RISCV_FLOAT_ABI_SINGLE;
+ break;
+ case RISCVABI::ABI_ILP32D:
+ case RISCVABI::ABI_LP64D:
+ EFlags |= ELF::EF_RISCV_FLOAT_ABI_DOUBLE;
+ break;
+ case RISCVABI::ABI_ILP32E:
+ EFlags |= ELF::EF_RISCV_RVE;
+ break;
+ case RISCVABI::ABI_Unknown:
+ llvm_unreachable("Improperly initialised target ABI");
+ }
+
+ MCA.setELFHeaderEFlags(EFlags);
+}
+
namespace {
class RISCVELFStreamer : public MCELFStreamer {
static std::pair<unsigned, unsigned> getRelocPairForSize(unsigned Size) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index 7ce7dafb8ca1f..eb2759f2c217f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -29,6 +29,7 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
SmallVector<AttributeItem, 64> Contents;
MCSection *AttributeSection = nullptr;
+ const MCSubtargetInfo &STI;
AttributeItem *getAttributeItem(unsigned Attribute) {
for (size_t i = 0; i < Contents.size(); ++i)
@@ -103,6 +104,8 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoRVC() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
+
+ void finish() override;
};
MCELFStreamer *createRISCVELFStreamer(MCContext &C,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 1580c55947ff3..165ec7c5d19ae 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -79,7 +79,17 @@ static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
if (CPU.empty() || CPU == "generic")
CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
- return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+
+ MCSubtargetInfo *STI =
+ createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+
+ // Check if Feature string is valid
+ auto ISAInfo =
+ RISCVFeatures::parseFeatureBits(TT.isArch64Bit(), STI->getFeatureBits());
+ if (!ISAInfo)
+ report_fatal_error(ISAInfo.takeError());
+ else
+ return STI;
}
static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 78a9e5838aa44..349116d6b106a 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -38,6 +38,10 @@ void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
unsigned IntValue,
StringRef StringValue) {}
+void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
+ assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
+ TargetABI = ABI;
+}
void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
if (STI.hasFeature(RISCV::FeatureRV32E))
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index 171780d94ce79..6f09016139b03 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -9,6 +9,7 @@
#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVTARGETSTREAMER_H
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVTARGETSTREAMER_H
+#include "RISCV.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
@@ -17,6 +18,8 @@ namespace llvm {
class formatted_raw_ostream;
class RISCVTargetStreamer : public MCTargetStreamer {
+ RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
+
public:
RISCVTargetStreamer(MCStreamer &S);
void finish() override;
@@ -36,6 +39,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
StringRef StringValue);
void emitTargetAttributes(const MCSubtargetInfo &STI);
+ void setTargetABI(RISCVABI::ABI ABI);
+ RISCVABI::ABI getTargetABI() const { return TargetABI; }
};
// This part is for ascii assembly output
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 9fed6e7baadc1..7d1ec2a93fadc 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -38,12 +38,13 @@ STATISTIC(RISCVNumInstrsCompressed,
namespace {
class RISCVAsmPrinter : public AsmPrinter {
- const MCSubtargetInfo *STI;
+ const MCSubtargetInfo *MCSTI;
+ const RISCVSubtarget *STI;
public:
explicit RISCVAsmPrinter(TargetMachine &TM,
std::unique_ptr<MCStreamer> Streamer)
- : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) {}
+ : AsmPrinter(TM, std::move(Streamer)), MCSTI(TM.getMCSubtargetInfo()) {}
StringRef getPassName() const override { return "RISCV Assembly Printer"; }
@@ -68,6 +69,8 @@ class RISCVAsmPrinter : public AsmPrinter {
void emitStartOfAsmFile(Module &M) override;
void emitEndOfAsmFile(Module &M) override;
+ void emitFunctionEntryLabel() override;
+
private:
void emitAttributes();
};
@@ -170,7 +173,8 @@ bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
MCSubtargetInfo &NewSTI =
OutStreamer->getContext().getSubtargetCopy(*TM.getMCSubtargetInfo());
NewSTI.setFeatureBits(MF.getSubtarget().getFeatureBits());
- STI = &NewSTI;
+ MCSTI = &NewSTI;
+ STI = &MF.getSubtarget<RISCVSubtarget>();
SetupMachineFunction(MF);
emitFunctionBody();
@@ -193,7 +197,14 @@ void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
void RISCVAsmPrinter::emitAttributes() {
RISCVTargetStreamer &RTS =
static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
- RTS.emitTargetAttributes(*STI);
+ RTS.emitTargetAttributes(*MCSTI);
+}
+
+void RISCVAsmPrinter::emitFunctionEntryLabel() {
+ AsmPrinter::emitFunctionEntryLabel();
+ RISCVTargetStreamer &RTS =
+ static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
+ RTS.setTargetABI(STI->getTargetABI());
}
// Force static initialization.
diff --git a/llvm/test/CodeGen/RISCV/module-target-abi2.ll b/llvm/test/CodeGen/RISCV/module-target-abi2.ll
index 8664c9add0691..f5fc69c2d28a2 100644
--- a/llvm/test/CodeGen/RISCV/module-target-abi2.ll
+++ b/llvm/test/CodeGen/RISCV/module-target-abi2.ll
@@ -8,8 +8,7 @@
; RV32IF-ILP32: -target-abi option != target-abi module flag
-; FLAGS: Flags: 0x0
-; // this should be "Flags :0x2, single-float ABI", it will be fixed later.
+; FLAGS: Flags: 0x2, single-float ABI
define float @foo(i32 %a) nounwind #0 {
; DEFAULT: # %bb.0:
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