[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/float-fcmp-strict.ll:72
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
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khchen wrote:
> It seems no any benefits in this case, is it expected?
sgtz ---->slt rd, X0, rs2
slt rd, 0 rs2 ---> slti + xori 
which can reduce the usage of one register


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https://reviews.llvm.org/D122051