[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/arith-with-overflow.ll:32
+; RV32I-NEXT:    slt a0, a3, a0
+; RV32I-NEXT:    slti a1, a1, 1
+; RV32I-NEXT:    xori a1, a1, 1
----------------
craig.topper wrote:
> Miss_Grape wrote:
> > craig.topper wrote:
> > > This looks like a regression
> > sgtz a3 a1 ------> slt  a3, X0, a1
> > slt a3, X0, a1---->slti a1, a1, 1 + xori a1, a1, 1
> > I think the result of the above assembly conversion is correct， which can reduce the registers use.
> If a1 was free to use as a destination register then it could have been `sgtz a1, a1`. This patch just moved the slti+xor below the the sub. We could do the same thing with the sgtz but it wouldn't change the number of registers needed.
Do you want me to exclude scenarios where Imm == 0 ？


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  https://reviews.llvm.org/D122051/new/

https://reviews.llvm.org/D122051