[llvm-bugs] [Bug 49549] New: Expected an XLenVT or scalable vector types at this stage assert when building SIMD code on RISCV

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https://bugs.llvm.org/show_bug.cgi?id=49549

            Bug ID: 49549
           Summary: Expected an XLenVT or scalable vector types at this
                    stage assert when building SIMD code on RISCV
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: RISC-V
          Assignee: unassignedbugs at nondot.org
          Reporter: simonas+llvm.org at kazlauskas.me
                CC: asb at lowrisc.org, llvm-bugs at lists.llvm.org

; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v
-riscv-v-vector-bits-min=128 < %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v
-riscv-v-vector-bits-min=128 < %s
define <4 x i1> @test_srem_vec(<4 x i32> %X) nounwind {
  %srem = srem <4 x i32> %X, <i32 9, i32 9, i32 -9, i32 -9>
  %cmp = icmp ne <4 x i32> %srem, <i32 3, i32 -3, i32 3, i32 -3>
  ret <4 x i1> %cmp
}

will fail when -DLLVM_ENABLE_ASSERTIONS=1 build of LLVM is used to run these
test cases.

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