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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Expected an XLenVT or scalable vector types at this stage assert when building SIMD code on RISCV"
href="https://bugs.llvm.org/show_bug.cgi?id=49549">49549</a>
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<th>Summary</th>
<td>Expected an XLenVT or scalable vector types at this stage assert when building SIMD code on RISCV
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: RISC-V
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>simonas+llvm.org@kazlauskas.me
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<th>CC</th>
<td>asb@lowrisc.org, llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v
-riscv-v-vector-bits-min=128 < %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v
-riscv-v-vector-bits-min=128 < %s
define <4 x i1> @test_srem_vec(<4 x i32> %X) nounwind {
%srem = srem <4 x i32> %X, <i32 9, i32 9, i32 -9, i32 -9>
%cmp = icmp ne <4 x i32> %srem, <i32 3, i32 -3, i32 3, i32 -3>
ret <4 x i1> %cmp
}
will fail when -DLLVM_ENABLE_ASSERTIONS=1 build of LLVM is used to run these
test cases.</pre>
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